14.6.17 DnTCM Fault Syndrome Register, n = 0,1
Note:
- Writes to this read-only register cause a bus error.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | DFLTSYNn |
| Offset: | 0x40 + n*0x10 [n=0..1] |
| Reset: | 0x00000000 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| ERR2 | ERR1 | SECSYN8 | |||||||
| Access | R | R | R | ||||||
| Reset | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SECSYN7 | SECSYN6 | SECSYN5 | SECSYN4 | SECSYN3 | SECSYN2 | SECSYN1 | SECSYN0 | ||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 15 – ERR2 Double Bit Error
| Value | Description |
|---|---|
| 0 | Not a Double bit error |
| 1 | A Double Bit error |
Bit 14 – ERR1 Single Bit Error
| Value | Description |
|---|---|
| 0 | Not a Single bit error |
| 1 | A Single Bit error |
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8 – SECSYNn ECC SECDED Error Capture Syndrome Bit n, n = 0,..8
ECC SECDED Syndrome bits read at the address defined by FLTADR.