37.9.2 USB Transmit Endpoint n Hub Address Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | TXHUBADDREP |
| Offset: | 0x1082 + n*0x08 [n=0..7] |
| Reset: | 0x0000 |
| Property: | Read/Write |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| MULTTRANS | TXHUBADDR[6:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 7 – MULTTRANS TX Hub Multiple Translators Bit
| Value | Description |
|---|---|
| 0 | The USB 2.0 hub has a single transaction translator |
| 1 | The USB 2.0 hub has multiple transaction translators |
Bits 6:0 – TXHUBADDR[6:0] TX Hub Address Bits
When a Low-Speed or Full-Speed device is connected to this endpoint via a Hi-Speed USB 2.0 hub, these bits record the address of the USB 2.0 hub.