40.8.5 SDHC_Transfer Mode Register
This register is used to control data transfers. The user shall set this register before issuing a command which transfers data (refer to bit DPSEL in SDHC_CR), or before issuing a Resume command. The user must save the value of this register when the data transfer is suspended (as a result of a Suspend command) and restore it before issuing a Resume command. To prevent data loss, this register cannot be written while data transactions are in progress. Writes to this register are ignored when bit SDHC_PSR.CMDINHD is '1'.
| MSBSEL | BCEN | SDHC_BCR.BLKCNT | Function |
|---|---|---|---|
| 0 | Don’t care | Don’t care | Single Transfer |
| 1 | 0 | Don’t care | Infinite Transfer |
| 1 | 1 | Not Zero | Multiple Transfer |
| 1 | 1 | Zero | Stop Multiple Transfer |
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | TMR |
| Offset: | 0x0C |
| Reset: | 0x0000 |
| Property: | - |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| MSBSEL | DTDSEL | ACMDEN[1:0] | BCEN | DMAEN | |||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
Bit 5 – MSBSEL Multi/Single Block Selection
Write this bit to '1' when issuing multiple-block transfer commands using DAT line(s). For any other commands, write this bit to 0. If this bit is 0, it is not necessary to write SDHC_BCR to '1'.
Bit 4 – DTDSEL Data Transfer Direction Selection
This bit defines the direction of the DAT lines data transfers. Write this bit to '1' to transfer data from the device (SD Card/SDIO/e.MMC) to the peripheral. Write this bit to '0' for all other commands.
| Value | Name | Description |
|---|---|---|
| 0 | WRITE | Writes data from the peripheral to the device. |
| 1 | READ | Reads data from the device to the peripheral. |
Bits 3:2 – ACMDEN[1:0] Auto Command Enable
- Auto CMD12: when the ACMDEN field is set to 1, the peripheral issues CMD12 automatically when the last block transfer is completed. An Auto CMD12 error is indicated to SDHC_ACESR. Auto CMD12 is not enabled if the command does not require CMD12.
- Auto CMD23: when the ACMDEN field is set to 2, the peripheral issues a CMD23 automatically before issuing a command specified in SDHC_CR.
- A memory card that supports CMD23 (SCR[33] = 1)
- If DMA is used, it must be ADMA (SDMA not supported).
- Only CMD18 or CMD25 is issued.
Auto CMD23 can be used with or without ADMA. By writing SDHC_CR, the peripheral issues a CMD23 first and then issues a command specified by the SDHC_CR.CMDIDX field. If CMD23 response errors are detected, the second command is not issued. A CMD23 error is indicated in SDHC_ACESR. The CMD23 argument (32-bit block count value) is defined in SDHC_SSAR.
This field determines the use of auto command functions.
| Value | Name | Description |
|---|---|---|
| 0 | DISABLED |
Auto Command Disabled |
| 1 | CMD12 |
Auto CMD12 Enabled |
| 2 | CMD23 |
Auto CMD23 Enabled |
| 3 | Reserved |
Reserved |
Bit 1 – BCEN Block Count Enable
This bit is used to enable SDHC_BCR, which is only relevant for multiple block transfers. When this bit is 0, SDHC_BCR is disabled, which is useful when executing an infinite transfer . If an ADMA2 transfer is more than 65535 blocks, this bit is set to 0 and the data transfer length is designated by the Descriptor Table.
| Value | Name | Description |
|---|---|---|
| 0 | DISABLED | Block count is disabled |
| 1 | ENABLED | Block count is enabled |
Bit 0 – DMAEN DMA Enable
This bit enables the DMA functionality described in section “Supporting DMA” in “SD Host Controller Simplified Specification V3.00” . DMA can be enabled only if it is supported as indicated by the bit SDHC_CA0R.ADMA2SUP. One of the DMA modes can be selected using the field SDHC_HC1R.DMASEL. If DMA is not supported, this bit is meaningless and then always reads 0. When this bit is set to 1, a DMA operation begins when the user writes to the upper byte of SDHC_CR.
| Value | Name | Description |
|---|---|---|
| 0 | DISABLED | DMA functionality is disabled |
| 1 | ENABLED | DMA functionality is enabled |