40.8.26 SDHC Capabilities 1 Register
Note: The Capabilities 1 Register is not
supposed to be written by the user.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CA1R |
| Offset: | 0x44 |
| Reset: | 0x00000070 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| CLKMULT[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DRVDSUP | DRVCSUP | DRVASUP | DDR50SUP | SDR104SUP | SDR50SUP | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 23:16 – CLKMULT[7:0] Clock Multiplier
This field indicates the multiplier factor between the Base Clock (BASECLK) used for the Divided Clock Mode and the Multiplied Clock (MULTCLK) used for the Programmable Clock mode (refer to SDHC_CCR).
Reading this field to 0 means that the Programmable Clock mode is not supported.
Bit 6 – DRVDSUP Driver Type D Support
| Value | Description |
|---|---|
| 0 |
Driver type D is not supported. |
Bit 5 – DRVCSUP Driver Type C Support
| Value | Description |
|---|---|
| 0 |
Driver type C is not supported. |
Bit 4 – DRVASUP Driver Type A Support
| Value | Description |
|---|---|
| 0 |
Driver type A is not supported. |
Bit 2 – DDR50SUP DDR50 Support
| Value | Description |
|---|---|
| 0 |
DDR50 mode is not supported. |
Bit 1 – SDR104SUP SDR104 Support
| Value | Description |
|---|---|
| 0 |
SDR104 mode is not supported. |
| 1 |
SDR104 mode is supported. |
Bit 0 – SDR50SUP SDR50 Support
| Value | Description |
|---|---|
| 0 |
SDR50 mode is not supported. |
| 1 |
SDR50 mode is supported. |