PIC32CZ CA80/CA90 Family

37.11.8 Host Endpoint 1-7 Polling Interval Register

Table 37-72. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	RXINTERVAL
Offset:	0x101D
Reset:	0x0000
Property:	PAC Write-Protection


Bit	7	6	5	4	3	2	1	0
	RXPOLLINGINTERVAL[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 7:0 – RXPOLLINGINTERVAL[7:0] Endpoint RX Polling Interval/NAK Limit bits

For Interrupt and Isochronous transfers, this field defines the polling interval for the endpoint. For Bulk end- points,this field sets the number of frames/microframes after which the endpoint should time out on receiving a stream of NAK responses.

The following table describes the valid values and interpretation for these bits:


Transfer Type	Speed	Valid Values (m)	Interpretation
Interrupt	Low/Full	0x01 to 0xFF	Polling interval is 'm' frames.
	High	0x01 to 0x10	Polling interval is 2^(m-1) frames.
Isochronous	Full or High	0x01 to 0x10	Polling interval is 2^(m-1) frames/microframes.
Bulk	Full or High	0x02 to 0x10	NAK limit is 2^(m-1) frames/microframes. A value of '`0`' or '`1`' disables the NAK time-out function.

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