45.6.4 Interrupt Flag Status and Clear

Note:
  1. Access to this register is limited to 32-bit width. Byte level access is not allowed.
  2. Reserved bits must always be written as ‘0’.
  3. Interrupt flags must be cleared and then read back to confirm they are cleared before exiting the ISR to avoid double interrupts.
Table 45-4. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit
Name: INTFLAG
Offset: 0x0C
Reset: 0x00000000
Property: -

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
       DRPERR 
Access R/WR/W 
Reset 00 

Bit 1 – DRP Data Remanence Prevention Complete Interrupt

This flag is set when the data remanence prevention routine has completed, and an interrupt request will be generated if INTENSET.DRP bit (INTENSET <1>) is set to '1'.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit clears the data remanence prevention complete interrupt flag.

Bit 0 – ERR TRAM Read Error Interrupt

This flag is set when an error is detected in the TRAM readout, and an interrupt request will be generated if INTENSET.ERR bit (INTENSET <0>) is set to '1'.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit clears the TRAM read error interrupt flag.