45.6.6 Synchronization Busy

Note: Access to this register is limited to 32-bit width. Byte level access is not allowed.
Table 45-6. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit
Name: SYNCBUSY
Offset: 0x14
Reset: 0x00000000
Property: -

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
       ENABLESWRST 
Access RR 
Reset 00 

Bit 1 – ENABLE Enable

ValueDescription
0Write synchronization for CTRLA.ENABLE bit (CTRLA <1>) bit is complete.
1Write synchronization for CTRLA.ENABLE bit (CTRLA <1>) bit is ongoing.

Bit 0 – SWRST Software Reset Synchronization Busy Status

This bit will set in two ways:

  • Writing ‘1’ to CTRLA.SWRST bit (CTRLA <0>)
  • A tamper event can occur when CTRLA.TAMPERS (CTRLA <4>) = ‘1’ (i.e., Tamper erase is enabled)
ValueDescription
0Write synchronization for CTRLA.SWRST bit (CTRLA <0>) bit is complete.
1Write synchronization for CTRLA.SWRST bit (CTRLA <0>) bit is ongoing.