45.6.2 Interrupt Enable Clear

Note:
  1. Access to this register is limited to 32-bit width. Byte level access is not allowed.
  2. Reserved bits must always be written as ‘0’.
Table 45-2. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit
Name: INTENCLR
Offset: 0x04
Reset: 0x00000000
Property: PAC Write-Protection

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
       DRPERR 
Access R/WR/W 
Reset 00 

Bit 1 – DRP Data Remanence Prevention Complete Interrupt Enable

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit will clear the Data Remanence Prevention Complete Interrupt Enable bit, which disables the data remanence prevention complete interrupt. Reading this bit provides the following information.

ValueDescription
0Data remanence prevention complete interrupt is disabled.
1Data remanence prevention complete interrupt is enabled.

Bit 0 – ERR TRAM Read Error Interrupt Enable

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit will clear the TRAM Read Error Interrupt Enable bit, which disables the TRAM read error interrupt. Reading this bit provides the following information.

ValueDescription
0TRAM read error interrupt is disabled.
1TRAM read error interrupt is enabled.