22.6.4 Interrupt Enable Clear

This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set (INTENSET) register.
Table 22-6. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit
Name: INTENCLR
Offset: 0x04
Reset: 0x00
Property: PAC Write-Protection

Bit 76543210 
        EW 
Access R/W 
Reset 0 

Bit 0 – EW Early Warning Interrupt Disable

Writing a '0' to this bit has no effect.


Writing a '1' to this bit clears the Early Warning Interrupt Enable bit, which disables the Early Warning interrupt.

ValueDescription
0The Early Warning interrupt is disabled.
1The Early Warning interrupt is enabled.