22.6.3 Early Warning Control

Table 22-5. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit——
Name: EWCTRL
Offset: 0x02
Reset: x initially determined from NVM User Row after reset
Property: PAC Write-Protection, Enable-Protected

Bit 76543210 
     EWOFFSET[3:0] 
Access R/W/CFGR/W/CFGR/W/CFGR/W/CFG 
Reset xxxx 

Bits 3:0 – EWOFFSET[3:0] Early Warning Interrupt Time Offset

These bits determine the number of GCLK_WDT clock cycles between the start of the watchdog time-out period and the generation of the Early Warning interrupt. These bits are loaded from User Configuration FUCFG0 at start-up.

ValueDescription
0x08 GCLK_WDT clock cycles
0x116 GCLK_WDT clock cycles
0x232 GCLK_WDT clock cycles
0x364 GCLK_WDT clock cycles
0x4128 GCLK_WDT clock cycles
0x5256 GCLK_WDT clock cycles
0x6512 GCLK_WDT clock cycles
0x71024 GCLK_WDT clock cycles
0x82048 GCLK_WDT clock cycles
0x94096 GCLK_WDT clock cycles
0xA8192 GCLK_WDT clock cycles
0xB - 0xFReserved