22.6.8 Clear
Note: This register is
write-synchronized: SYNCBUSY.CLEAR must be checked to ensure the CLEAR register
synchronization is complete.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CLEAR |
| Offset: | 0x0C |
| Reset: | 0x00 |
| Property: | Write-Synchronized |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CLEAR[7:0] | |||||||||
| Access | W | W | W | W | W | W | W | W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 7:0 – CLEAR[7:0] Watchdog Clear
In Normal mode, writing 0xA5 to this register during the watchdog time-out period will clear the Watchdog Timer and the watchdog time-out period is restarted.
In Window mode, any writing attempt to this register before the time-out period started (i.e., during TOWDTW) will issue an immediate system Reset. Writing 0xA5 during the time-out period TOWDT will clear the Watchdog Timer and the complete time-out sequence (first TOWDTW then TOWDT) is restarted.
In both modes, writing any other value than 0xA5 will issue an immediate system Reset.
Note: This bit field is
write-synchronized: SYNCBUSY.CLEAR must be checked to ensure the CLEAR.CLEAR
synchronization is complete.