26.6.1 Voltage Regulators

The main regulators output supply level is automatically defined by the sleep mode selected in the Power Manager module.

Additional regulators are disabled by default and can be enabled and disabled by writing the corresponding AVREGEN[n] bit in the VREGCTRL register. There are three additional regulators: n = 0 for USB-PHY0, n = 1 for USB-PHY1, and n = 2 for PLL-0.

The VDDCORE supplies (VDDCORE_SW, VDDCORE_RAM, VDDCORE_BU, VDDCORE_USB/VDDCORE_PLL if enabled in standby mode).

Additional regulator voltage level is OFF while in sleep mode equal or deeper than standby mode to reduce consumption, meaning that domain driven by this regulator (USB or PLL) cannot be used in standby mode. This default behavior can be changed by configuring the ”Additional Voltage Regulator Configuration” bits field in the VREGCTRL CONTROL register (VREGCTRL.AVREGCFGn n = 0 for USB-PHY0, n = 1 for USB-PHY1, and n = 2 for PLL.).

This is highly recommended to activate charge pumps when VDDA/VDDIO is too low. The control of Charge pump n (n = 0,1,2) is managed by setting the corresponding bit in VREGCTRL.CPEN[2:0]. When CPEN[n] bit is set, the enable and auto-enable bits of the charge pump[N] are set. In standby mode, the charge pumps are automatically turned OFF except if a consumer (PTC/ ADC or AC) of the charge pump is requesting the charge pump.