30.8.4 Memory Interface Block

The Memory Interface (MIF) block implements a bridge between the I/O and the CTB or DBB interfaces.

CTR Access

The MIF block allows the HC to directly access the external Channel Table RAM (CTR) when MADR.TB is cleared. Any write to the MADR register triggers a single read or write cycle. Reading from the MADR register does not initiate read/write access.

Figure 30-5. MIF CTR Read and Write Flow Diagrams

Direct CTR Writes

For a direct write of the CTR, the HC first loads the 128-bit data entry into the MDAT0–3 registers. Bitwise write enable control is available via the MDWE0–3 registers.

After the MDATn and MDWEn registers are set up, a write cycle is initiated by writing the address and control information to MADR as follows:

  • MADR.WNR = 1
  • MADR.TB = 0
  • MADR.ADDR[7:0] = 8-bit Target Address

The MIF block sets MCTL.XCMP = 1 to inform the HC when the write is complete.

Direct CTR Reads

For a direct read of the CTR, the HC initiates a read cycle by writing the address and control information to MADR as follows:

  • MADR.WNR = 0
  • MADR.TB = 0
  • MADR.ADDR[7:0] = 8-bit Target Address

The MIF block sets MCTL.XCMP = 1 to inform the HC when the read is complete. The HC can then read the 128-bit data entry from the MDAT0–3 registers.

CTR Addressing

The CTR is addressed as a 128-bit wide value. However, the MIF block can only access 32 bits of the addressed CTR data in a single access. Therefore, four 32-bit accesses through the MIF block are required to access a single 128-bit value (e.g. CDT entry).

To access a 16-bit CAT entry in the CTR, only a single access through the MIF is required. For example, to load a CAT61 entry for an isochronous Tx channel with mute and flow control enabled:

  • Write MDAT2 = 7B070000h (assumes Connection Label = 7)
  • MDWE2 = FFFF0000h (bitwise write enable for 16 msbs; 
assumes MDWE0/1/3 =00000000h)
  • MADR = 80000087h (write CTR address 87h)

DBR Access

The MIF block allows the HC to access the external Data Buffer RAM (DBR) directly when MADR.TB is set. Any write to the MADR triggers a single read or write cycle. Reading from the MADR register does not initiate read/write access.

Figure 30-6. MIF DBR Read and Write Flow Diagrams

Direct DBR Writes

For a direct write of the DBR, the HC first loads the 8-bit data entry into the MDAT0 register at bits[7:0]. MDAT1–3 and MDWE0–3 are not used for DBR access.

After the MDAT0 register is set up, a write cycle is initiated by writing the address and control information to MADR as follows:

  • MADR.WNR = 1
  • MADR.TB = 1
  • MADR.ADDR[13:0] = 14-bit Target Address

The MIF block sets MCTL.XCMP = 1 to inform the HC when the write is complete.

Direct DBR Reads

For a direct read of the DBR, the HC initiates a read cycle by writing the address and control information to MADR as follows:

  • MADR.WNR = 0
  • MADR.TB = 1
  • MADR.ADDR[13:0] = 14-bit target address

The MIF block sets MCTL.XCMP = 1 to inform the HC when the read is complete. The HC can then read the 8-bit data entry from the MDAT0 register at bits[7:0].