38.5 Peripheral Dependencies
| Peripheral Name | Base Address | NVIC IRQ Index:Source | MCLK AXI/APB Clk Index | GCLK Peripheral Channel Index : Clock | PAC Peripheral Identifier (PAC.WRCTRL) | DMA Trigger Index:Source (DMAC.CHCTRLB) | Power Domain |
|---|---|---|---|---|---|---|---|
| CAN0 | 0x4506 0000 |
194 : LINE0, LINE1, or ERROR | MCLK.CLKMSK1[24] | GCLK.PCHCTRL[46] | 48 INTFLAGB[16] |
83 : DMA CAN0 Debug | VDDREG |
| CAN1 | 0x4606 0000 | 195: LINE0, LINE1, or ERROR | MCLK.CLKMSK1[25] | GCLK.PCHCTRL[47] |
49 INTFLAGB[17] |
84 : DMA CAN1 Debug | VDDREG |
| CAN2 | 0x4606 2000 | 196: LINE0, LINE1, or ERROR | MCLK.CLKMSK1[26] | GCLK.PCHCTRL[48] |
50 INTFLAGB[18] |
85 : DMA CAN2 Debug | VDDREG |
| CAN3 | 0X4586 0000 | 197: LINE0, LINE1, or ERROR | MCLK.CLKMSK1[27] | GCLK.PCHCTRL[49] |
51 INTFLAGB[19] |
86 : DMA CAN3 Debug | VDDREG |
| CAN4 | 0x4506 2000 | 198: LINE0, LINE1, or ERROR | MCLK.CLKMSK1[28] | GCLK.PCHCTRL[50] |
52 INTFLAGB[20] |
87 : DMA CAN4 Debug | VDDREG |
| CAN5 | 0x4686_0000 | 199: LINE0, LINE1, or ERROR | MCLK.CLKMSK1[29] | GCLK.PCHCTRL[51] |
53 INTFLAGB[21] |
88 : DMA CAN5 Debug | VDDREG |