31.3.4 Clocks

The FCR peripheral bus clock (CLK_FCR_APB) can be enabled and disabled in the Main Clock Controller.

The FCR data bus clock (CLK_FCR_AHB) can be enabled and disabled in the Main Clock Controller.

The FCR also requires an on-chip 8 MHz clock source that is automatically configured without application assistance. The CLK_GEN_FCW is derived by dividing the 48 MHz trimmed internal RC oscillator by 6. This clock is used by the Period Clock (PerCLK) to provide additional delay between the stop and start of the CRC engine.