31.3.5 Concurrent Access

In order to permit code execution from one Flash panel while writing (or erasing) another, the FCR detects and arbitrates access conflicts between the Flash Write Controller (FCW), System read requests, and internal read requests.

When a Flash panel can no longer be read because it is actively being written or erased, the FCR’s Arbiter is signaled accordingly. Read accesses from the system bus are compared to the panel address ranges and allocated accordingly within the panel arbiter.

The FCR’s Arbiter permits system reads to access any panel, provided it is not being actively written or erased. The panel arbiter also permits concurrent read accesses to different panels.

If the system (CPU or other peripheral initiator) attempts to access a panel that is being actively written or erased, then the FCR’s Arbiter delays the data ready response to the initiator until such time that the FCW has completed its sequence (i.e. the FCW always has priority).