32.6.3.6 DMA Packet Buffer

The DMA uses packet buffers for both transmit and receive paths. This mode allows multiple packets to be buffered in both transmit and receive directions. This allows the DMA to withstand far greater access latencies on the AXI and make more efficient use of the AXI bandwidth. There are two modes of operation—Full Store and Forward and Partial Store and Forward.

As described above, the DMA can be programmed into a low latency mode, known as Partial Store and Forward. For further details of this mode, see the related Links.

When the DMA is in full store and forward mode, full packets are buffered which provides the possibility to:

  • Discard packets with error on the receive path before they are partially written out of the DMA, therefore saving AXI bus bandwidth and driver processing overhead,
  • Retry collided transmit frames from the buffer, therefore saving AXI bus bandwidth,
  • Implement transmit IP/TCP/UDP checksum generation offload.

With the packet buffers included, the structure of the GMAC data paths is shown in this image:

Figure 32-2. Data Paths with Packet Buffers Included