19.7.8 32 kHz External Crystal Oscillator (XOSC32K) Control

Table 19-9. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	XOSC32K
Offset:	0x1C
Reset:	0x00200080
Property:	PAC Write-Protection


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
			CGM[3:0]
Access			R/W	R/W	R/W	R/W
Reset			1	0	0	0


Bit	15	14	13	12	11	10	9	8
					STARTUP[3:0]
Access					R/W	R/W	R/W	R/W
Reset					0	0	0	0


Bit	7	6	5	4	3	2	1	0
	ONDEMAND					XTALEN	ENABLE
Access	R/W					R/W	R/W
Reset	1					0	0

Bits 21:18 – CGM[3:0] Control Gain Mode

These bits control the gain of the external crystal oscillator.

These bits are enable-protected.


Value	Name	Description
`0x0`	CGM0	The lower Control Gain Mode value
`0x1`	CGM1	A higher Control Gain Mode value than CGM0
`0x2`	CGM2	A higher Control Gain Mode value than CGM1
`0x3`	CGM3	A higher Control Gain Mode value than CGM2
`0x4`	CGM4	A higher Control Gain Mode value than CGM3
`0x5`	CGM5	A higher Control Gain Mode value than CGM4: Min Recommended for SF=3, ESR ≤ 100K Min Recommended for SF=5, ESR ≤ 60K
`0x6`	CGM6	A higher Control Gain Mode value than CGM5
`0x7`	CGM7	A higher Control Gain Mode value than CGM6
`0x8`	CGM8	A higher Control Gain Mode value than CGM7
`0x9`	CGM9	A higher Control Gain Mode value than CGM8
`0xA`	CGM10	A higher Control Gain Mode value than CGM9, ( Min Recommended for SF=5, ESR ≤ 100K)
`0xB`	CGM11	A higher Control Gain Mode value than CGM10
`0xC`	CGM12	A higher Control Gain Mode value than CGM11
`0xD`	CGM13	A higher Control Gain Mode value than CGM12
`0xE`	CGM14	A higher Control Gain Mode value than CGM13
`0xF`	CGM15	The highest Control Gain Mode value

Note:

These bits are enable-protected. They cannot be written to if XOSC32K.ENABLE = 1.

Bits 11:8 – STARTUP[3:0] Oscillator Start-Up Time

These bits select the start-up time for the XOSC32K oscillator. The OSCULP32K oscillator is used to clock the start-up counter. The given time assumes an XOSC32K crystal frequency of 32.768 kHz.

After the XOSC32K.STARTUP time has expired, the XOSC32K clock is released internally after the selected programmable startup clock cycles plus 3 additional XOSC32 periods. The Clock Fail Detect (CFD) monitoring also starts when the clock is released for internal use. The user selected start-up time must equal or exceed the start-up time defined in the electrical characteristics.


STARTUP[2:0]	OSCULP32K Clock Cycles	Plus	XOSC32K Clock Cycles	Equal	Approximate Equivalent Time
0x0	1	+	3	=	~122 µs
0x1	16	+	3	=	~580 µs
0x2	32	+	3	=	~1.07 ms
0x3	2048	+	3	=	~62.6 ms
0x4	4096	+	3	=	~125.1 ms
0x5	8192	+	3	=	~250.1 ms
0x6	16384	+	3	=	~500.1 ms
0x7	32768	+	3	=	~1s
0x8	65536	+	3	=	~2s
0x9	131072	+	3	=	~4s
0xA	262144	+	3	=	~8s
0xB – 0xF	---	---	---	---	Reserved

Note: These bits are enable-protected. They cannot be written to if XOSC32K.ENABLE = 1.

These bits are valid only when XOSC32K.XTALEN = 1, crystal XOSC32K selected.

Bit 7 – ONDEMAND On Demand Control

This bit controls how the XOSC32K behaves when a peripheral clock request is detected.

Note: This bit is enable-protected. It cannot be written to if XOSC32K.ENABLE = 1.

Value	Description
0	XOSC32K always run
1	Only run if requested by a peripheral

Bit 2 – XTALEN Crystal Oscillator Enable

This bit controls the connections between the I/O pads and the external clock or crystal oscillator.