19.7.6 Clock Failure Detector Control

Table 19-7. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit——
Name: CFDCTRL
Offset: 0x14
Reset: 0x00000000
Property: PAC Write-Protection

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
      CFDPRESCSWBACKCFDEN 
Access R/WR/WR/W 
Reset 000 

Bit 2 – CFDPRESC Clock Failure Detector Prescaler

This bit selects the prescaler for the Clock Failure Detector.
ValueDescription
0The CFD safe clock frequency is the OSCULP32K frequency
1The CFD safe clock frequency is the OSCULP32K frequency divided by 2

Bit 1 – SWBACK Clock Switch Back

This bit controls the XOSC32K output switch back to the external clock or crystal oscillator in case of clock recovery.
ValueDescription
0The clock switch is disabled.
1The clock switch is enabled. This bit is reset when the XOSC32K output is switched back to the external clock or crystal oscillator.

Bit 0 – CFDEN Clock Failure Detector Enable

This bit selects the Clock Failure Detector state.
Note: After setting CFDEN to enable clock failure detection, STATUS.XOSC32KFAIL will always be set. This first detection must be ignored. Subsequent setting of this bit will indicate actual clock failure events.
ValueDescription
0The CFD is disabled.
1The CFD is enabled.