29.6.1.1 Initialization

The EIC must be initialized in the following order:

  1. Enable CLK EICAPB.
  2. If required, configure the NMI by writing the Non-Maskable Interrupt Control (NMICTRL) register.
  3. Enable GCLK EIC or CLK ULP32K when one of the following external interrupt, EIC_EXTINTx pins, modes is selected:
    • EIC_EXTINT pin filtering
    • EIC_EXTINT pin synchronous edge detection
    • EIC_EXTINT pin de-bouncing
    • GCLK EIC is used when a frequency higher than 32 kHz is required for filtering
    • CLK ULP32K is recommended when power consumption is the priority
  4. For CLK ULP32K write a '1' to the Clock Selection bit in the Control A register (CTRLA.CKSEL).
  5. Configure the EIC input sense and filtering by writing the Configuration n register (CONFIG).
  6. Optionally, enable the Aaynchronous mode.
  7. Optionally, enable the Debounce mode.
  8. Enable the EIC by writing a '1' to CTRLA.ENABLE.
The following bits are enable-protected, meaning that they can only be written when the EIC is disabled (CTRLA.ENABLE=0):
  • Clock Selection bit in Control A register (CTRLA.CKSEL)
The following registers are enable-protected:
  • Event Control register (29.7.3 EVCTRL)
  • Configuration n register (29.7.8 CONFIG).
  • External Interrupt Asynchronous Mode register (29.7.7 ASYNCH)
  • Debouncer Enable register (29.7.10 DEBOUNCEN)
  • Debounce Prescaler register (29.7.11 DPRESCALER)

Enable-protected bits in the CTRLA register can be written at the same time when setting CTRLA.ENABLE to '1', but not at the same time as CTRLA.ENABLE is being cleared.

Enable-protection is denoted by the "Enable-Protected" property in the register description.