33.7.12 Channel n Status
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CHSTATUSn |
| Offset: | 0x27 + n*0x08 [n=0..7] |
| Reset: | 0x01 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| BUSYCH | RDYUSR | ||||||||
| Access | R | R | |||||||
| Reset | 0 | 0 |
Bit 1 – BUSYCH Busy Channel
This bit is cleared when channel is idle.
This bit is set if an event on channel has not been handled by all event users connected to channel.
When the event channel path is asynchronous, this bit is always read '0'.
Bit 0 – RDYUSR Ready User
This bit is cleared when at least one of the event users connected to the channel is not ready.
This bit is set when all event users connected to channel are ready to handle incoming events on the channel.
When the event channel path is asynchronous, this bit is always read ‘0’.