33.7.6 Busy Channels

Table 33-7. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit
Name: BUSYCH
Offset: 0x18
Reset: 0x00000000
Property: -

Bit 3130292827262524 
 BUSYCH31BUSYCH30BUSYCH29BUSYCH28BUSYCH27BUSYCH26BUSYCH25BUSYCH24 
Access RRRRRRRR 
Reset 00000000 
Bit 2322212019181716 
 BUSYCH23BUSYCH22BUSYCH21BUSYCH20BUSYCH19BUSYCH18BUSYCH17BUSYCH16 
Access RRRRRRRR 
Reset 00000000 
Bit 15141312111098 
 BUSYCH15BUSYCH14BUSYCH13BUSYCH12BUSYCH11BUSYCH10BUSYCH9BUSYCH8 
Access RRRRRRRR 
Reset 00000000 
Bit 76543210 
 BUSYCH7BUSYCH6BUSYCH5BUSYCH4BUSYCH3BUSYCH2BUSYCH1BUSYCH0 
Access RRRRRRRR 
Reset 00000000 

Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – BUSYCHx Busy Channel x

This bit is set if an event occurs on channel x has not been handled by all event users connected to channel x.

This bit is cleared when channel x is idle.

When the event channel x path is asynchronous, this bit is always read '0'.