33.7.8 Channel n Control
This register allows the user to configure channel n. To write to this register, do a single, 32-bit write of all the configuration data.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CHANNELn |
| Offset: | 0x20 + n*0x08 [n=0..7] |
| Reset: | 0x00008000 |
| Property: | PAC Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| ONDEMAND | RUNSTDBY | EDGSEL[1:0] | PATH[1:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 1 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| EVGEN[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 15 – ONDEMAND Generic Clock On Demand
| Value | Description |
|---|---|
| 0 | Generic clock for a channel is always on, if the channel is configured and generic clock source is enabled. |
| 1 | Generic clock is requested on demand while an event is handled |
Bit 14 – RUNSTDBY Run in Standby
This bit is used to define the behavior during standby sleep mode.
| Value | Description |
|---|---|
| 0 | The channel is disabled in standby sleep mode. |
| 1 | The channel is not stopped in standby sleep mode and depends on the CHANNEL.ONDEMAND bit. |
Bits 11:10 – EDGSEL[1:0] Edge Detection Selection
These bits set the type of edge detection to be used on the channel.
These bits must be written to zero when using the asynchronous path.
| Value | Name | Description |
|---|---|---|
| 0x0 | NO_EVT_OUTPUT | No event output when using the resynchronized or synchronous path |
| 0x1 | RISING_EDGE | Event detection only on the rising edge of the signal from the event generator |
| 0x2 | FALLING_EDGE | Event detection only on the falling edge of the signal from the event generator |
| 0x3 | BOTH_EDGES | Event detection on rising and falling edges of the signal from the event generator |
Bits 9:8 – PATH[1:0] Path Selection
These bits are used to choose which path will be used by the selected channel.
Note: The path choice can be limited
by the channel source. Only a channel with an index less than12, embeds
synchronous/resynchronous capabilities. The rest of available channels support
only asynchronous path selection.
Important:
- When synchronous or resynchronized path is enabled, event inversion feature in peripherals must not be enabled (EVCTRL.xxxINV = 0.
- To avoid spurious EVSYS detections, EVSYS must be write protected by configuring the WRCTRL register in the PAC before being used.
| Value | Name | Description |
|---|---|---|
| 0x0 | SYNCHRONOUS | Synchronous path |
| 0x1 | RESYNCHRONIZED | Resynchronized path |
| 0x2 | ASYNCHRONOUS | Asynchronous path |
| Other | - | Reserved |
Bits 7:0 – EVGEN[7:0] Event Generator Selection
These bits are used to choose the event generator to connect to the selected channel.
| Module Name | Name of Generator | Value | Description |
|---|---|---|---|
| SUPC | SUPC LVDET | 0 | - |
| OSCCTRL | XOSC FAIL | 1 | XOSC fail detection |
| OSC32KCTRL | XOSC32K_FAIL | 2 | XOSC32K fail detection |
| FREQM | DONE | 3 | - |
| WINMON | 4 | - | |
| RTC | RTC-PERx | 5-12 | RTC period x=0..7 |
| RTC-CMPx | 13-16 | RTC comparison x=0..3 | |
| RTC-TAMPER | 17 | RTC tamper detection | |
| RTC-OVF | 18 | RTC overflow | |
| RTC-PERD | 19 | RTC Daily Period | |
| EIC | EXTINTx | 20-35 | EIC external interrupt x=0..15 |
| PAC | PAC_ACCERR | 36 | PAC Access. error |
| DMA | DMAC_CHx | 37-52 | DMA channel x=0..15 |
| TCC0 | OVF | 53 | TCC0 Overflow |
| TRG | 54 | TCC0 Trigger Event | |
| CNT | 55 | TCC0 Counter | |
| MCx | 56-63 | TCC0 Match/Compare x=0..7 | |
| TCC1 | OVF | 64 | TCC1 Overflow |
| TRG | 65 | TCC1 Trigger Event | |
| CNT | 66 | TCC1 Counter | |
| MCx | 67-74 | TCC1 Match/Compare x=0..7 | |
| TCC2 | OVF | 75 | TCC2 Overflow |
| TRG | 76 | TCC2 Trigger Event | |
| CNT | 77 | TCC2 Counter | |
| MCx | 78- 83 | TCC2 Match/Compare x=0..5 | |
| TCC3 | OVF | 84 | TCC3 Overflow |
| TRG | 85 | TCC3 Trigger Event | |
| CNT | 86 | TCC3 Counter | |
| MCx | 87-88 | TCC3 Match/Compare x=0..1 | |
| TCC4 | OVF | 89 | TCC4 Overflow |
| TRG | 90 | TCC4 Trigger Event | |
| CNT | 91 | TCC4 Counter | |
| MCx | 92-93 | TCC4 Match/Compare x=0..1 | |
| TCC5 | OVF | 94 | TCC5 Overflow |
| TRG | 95 | TCC5 Trigger Event | |
| CNT | 96 | TCC5 Counter | |
| MCx | 97-98 | TCC5 Match/Compare x=0..1 | |
| TCC6 | OVF | 99 | TCC6 Overflow |
| TRG | 100 | TCC6 Trigger Event | |
| CNT | 101 | TCC6 Counter | |
| MCx | 102-103 | TCC6 Match/Compare x=0..1 | |
| TCC7 | OVF | 104 | TCC7 Overflow |
| TRG | 105 | TCC7 Trigger Event | |
| CNT | 106 | TCC7 Counter | |
| MCx | 107-108 | TCC7 Match/Compare x=0..1 | |
| TCC8 | OVF | 109 | TCC8 Overflow |
| TRG | 110 | TCC8 Trigger Event | |
| CNT | 111 | TCC8Counter | |
| MCx | 112-113 | TCC8 Match/Compare x=0..1 | |
| TCC9 | OVF | 114 | TCC9 Overflow |
| TRG | 115 | TCC9 Trigger Event | |
| CNT | 116 | TCC9 Counter | |
| MCx | 117-122 | TCC9 Match/Compare x=0..5 | |
| ADC | ADCx RESRDY | 123-126 | ADCx Ready x=0..3 |
| ADC CMPx | 127-130 | ADC Compare event x=0..3 | |
| AC | AC COMPx | 131-132 | AC Comparator, x=0..1 |
| AC WIN | 133 | AC0 Window | |
| PTC | EOC | 134 | PTC end of Conversion |
| WCOMP | 135 | PTC Window Compare | |
| GMAC | TSU_CMP | 136 | GMAC Time stamp CMP |
| TRNG | READY | 137 | TRNG ready |
Note:
- A = Asynchronous path, S = Synchronous path, R = Resynchronized path