23.8.8 Interrupt Flag Status and Clear
Note: Subsequent to an interrupt flag being cleared, the flag must be read back to verify
the clear before exiting the ISR. Failure to do this can result in duplicate interrupts.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | INTFLAG |
| Offset: | 0x0A |
| Reset: | 0x00 |
| Property: | – |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| WINMON | DONE | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
Bit 1 – WINMON Window Monitor
This flag is set on the next clock cycle after a match with the window monitor condition, and an interrupt request will be generated if INTENCLR/SET.WINMON is '1'.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the WINMON interrupt flag.
Bit 0 – DONE Measurement Done
This flag is set when the STATUS.BUSY bit has a one-to-zero transition.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the DONE interrupt flag.