2.2.2.1 Clock Configuration Procedure

Perform the following steps to configure PLLs and peripheral clocks for recommended values:

1. Launch the MCC configuration menu for the main project.
2. Open the Clock Diagram from the menu as shown in Clock Source Selection.
   Note: The sample applications are pre-configured with these values by default.
   1. Enable POSCMOD to HS (if not set).

      

   2. Select the input clock as POSC from the respective clock MUX for SPLLICLK and EWICLK as shown in the following figure.
   3. Click the Auto-Calculate button for each PLL block to set the proper divisor values to achieve the required output frequency.
   4. In all the example codes, the system clock (SYSCLK) is set to 200 MHz.

      

   Note: The following instructions are for specific use cases, where the configuration may need a modification. Generally, these configurations are done by default by Harmony and do not require a change for most of the cases.
3. Generate the peripheral clock (PBCLK1) as per the following requirements:
   1. Ensure from the Clock Diagram that the required frequencies are derived for peripheral clocks through the clock settings. Most of the peripheral clocks are SYSCLCK/2.
   2. Some applications may need to use 4 as the PBCLK3 divisor value (PB3DIV) to provide a 50 MHz clock for the required peripherals.

      

4. Save the settings and click on the button to generate the code.
   1. Once the code generation is successful, click on the Build Project button.
   2. The “Build Successful” message in the output window of MPLAB X IDE confirms successful compilation.