41.4.19 Configurable Logic Block (CLB) Characteristics

Table 41-25.
Standard Operating Conditions (unless otherwise stated)
Param No.	Sym.	Characteristic	Min.	Typ. †	Max.	Units	Conditions
CLB01*	T_BLE	Single BLE input to output propagation time	—	10	—	ns
CLB02*	T_{MIN_TRIG}	Input minimum high to low time to trigger BLE	—	5	—	ns
CLB02A*	T_{MIN_TRIG}	Input minimum low to high time to trigger BLE	—	8	—	ns
CLB03*	T_{EC_SU}	CLB Data Set-up time	—	10	—	ns
CLB04*	T_{EC_H}	CLB External Data Hold time	—	10	—	ns
CLB05*	T_{EC_DC}	CLB external clock duty cycle	—	50	—	%
CLB06*	F_{MAX_SYNC}	CLB module maximum clock frequency for synchronous applications	—	16	—	MHz
CLB07*	F_{MAX_ASYNC}	CLB module maximum switching frequency for asynchronous applications	—	100	—	MHz
CLB08*	T_CONFIG	CLB Configuration loading time	—	206	—	Instruction Cycles (T_CY)	MD = `01`, Burst Mode
* These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.