26.9.7 Event Control

Table 26-46. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
R Readable bit HC Cleared by Hardware(Grey cell)Unimplemented
W Writable bit HS Set by Hardware X Bit is unknown at Reset
K Write to clear S Software settable bit
Name: EVCTRL
Offset: 0x0A
Reset: 0x0000
Property: PAC Write-Protection, Enable-Protected

Bit 15141312111098 
   MCEO1MCEO0   OVFEO 
Access R/WR/WR/W 
Reset 000 
Bit 76543210 
   TCEITCINV EVACT[2:0] 
Access R/WR/WR/WR/WR/W 
Reset 00000 

Bits 12, 13 – MCEOx Match or Capture Channel x Event Output Enable [x = 1..0]

These bits enable the generation of an event for every match or capture on channel x.

ValueDescription
0Match/Capture event on channel x is disabled and will not be generated.
1Match/Capture event on channel x is enabled and will be generated for every compare/capture.

Bit 8 – OVFEO Overflow/Underflow Event Output Enable

This bit enables the Overflow/Underflow event. When enabled, an event will be generated when the counter overflows/underflows.

ValueDescription
0Overflow/Underflow event is disabled and will not be generated.
1Overflow/Underflow event is enabled and will be generated for every counter overflow/underflow.

Bit 5 – TCEI TC Event Enable

This bit is used to enable asynchronous input events to the TC.

ValueDescription
0Incoming events are disabled.
1Incoming events are enabled.

Bit 4 – TCINV TC Inverted Event Input Polarity

This bit inverts the asynchronous input event source.

ValueDescription
0Input event source is not inverted.
1Input event source is inverted.

Bits 2:0 – EVACT[2:0] Event Action

These bits define the event action the TC will perform on an event.

ValueNameDescription
0x0OFFEvent action disabled
0x1RETRIGGERStart, restart or retrigger TC on event
0x2COUNTCount on event
0x3STARTStart TC on event
0x4
0x5PPWPeriod captured in CC0, pulse width in CC1
0x6PWPPeriod captured in CC1, pulse width in CC0
0x7