26.9.3 Control B Clear

This register allows the user to clear bits in the CTRLB register without doing a read-modify-write operation. Changes in this register will also be reflected in the Control B Set register (CTRLBSET).

Table 26-40. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
R Readable bit HC Cleared by Hardware(Grey cell)Unimplemented
W Writable bit HS Set by Hardware X Bit is unknown at Reset
K Write to clear S Software settable bit——
Name: CTRLBCLR
Offset: 0x04
Reset: 0x00
Property: PAC Write-Protection, Read-Synchronized, Write-Synchronized

Bit 76543210 
 CMD[1:0]   ONESHOT DIR 
Access R/WR/WR/WR/W 
Reset 0000 

Bits 7:6 – CMD[1:0] Command

These bits are used for software control of the TC. The commands are executed on the next prescaled GCLK_TC clock cycle. When a command has been executed, the CMD bit group will be read back as zero.

Writing 0x0 to these bits has no effect.

Writing a '1' to any of these bits will clear the pending command.

Table 26-41. Command
ValueNameDescription
0x0NONENo action
0x1RETRIGGERForce a start, restart or retrigger
0x2STOPForce a stop
0x3-Reserved

Bit 2 – ONESHOT One-Shot on Counter

This bit controls one-shot operation of the TC.

Writing a '0' to this bit has no effect

Writing a '1' to this bit will disable one-shot operation.

ValueDescription
0The TC will wrap around and continue counting on an Overflow/Underflow condition.
1The TC will wrap around and stop on the next Underflow/Overflow condition.

Bit 0 – DIR Counter Direction

This bit is used to change the direction of the counter.

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will clear the bit and make the counter count up.

ValueDescription
0The timer/counter is counting up (incrementing).
1The timer/counter is counting down (decrementing).