26.9.11 Status
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | STATUS |
| Offset: | 0x0F |
| Reset: | 0x08 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SYNCBUSY | SLAVE | STOP | |||||||
| Access | R | R | R | ||||||
| Reset | 0 | 0 | 1 |
Bit 7 – SYNCBUSY Synchronization Busy
This bit is cleared when the synchronization of registers between the clock domains is complete.
This bit is set when the synchronization of registers between clock domains is started.
Bit 4 – SLAVE Client Status Flag
This bit is only available in 32-bit mode on the Client TC. The bit is set when the associated Host TC is set to run in 32-bit mode.
Bit 3 – STOP Stop Status Flag
This bit is set when the TC is disabled, on a Stop command, or on an overflow/underflow condition when the One-Shot bit in the Control B Set register (CTRLBSET.ONESHOT) is '1'.
| Value | Description |
|---|---|
| 0 | Counter is running. |
| 1 | Counter is stopped. |