15.7.3 Early Warning Interrupt Control

Table 15-6. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
R Readable bit HC Cleared by Hardware(Grey cell)Unimplemented
W Writable bit HS Set by Hardware X Bit is unknown at Reset
K Write to clear S Software settable bit——
Name: EWCTRL
Offset: 0x2
Reset: N/A - Loaded from NVM User Row at start-up
Property: Write-Protected, Enable-Protected

Bit 76543210 
     EWOFFSET[3:0] 
Access R/WR/WR/WR/W 
Reset xxxx 

Bits 3:0 – EWOFFSET[3:0] Early Warning Interrupt Time Offset

These bits determine the number of GCLK_WDT clocks in the offset from the start of the Watchdog Time-out period to when the Early Warning interrupt is generated. These bits are loaded from NVM User Row at start-up. Refer to NVM User Row Mapping for more details.

ValueDescription
0x08 clock cycles
0x116 clock cycles
0x232 clock cycles
0x364 clock cycles
0x4128 clock cycles
0x5256 clocks cycles
0x6512 clocks cycles
0x71024 clock cycles
0x82048 clock cycles
0x94096 clock cycles
0xA8192 clock cycles
0xB16384 clock cycles
0xC-0xFReserved