16.7.5 Interrupt Enable Set - MODE0
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | INTENSET |
| Offset: | 0x07 |
| Reset: | 0x00 |
| Property: | Write-Protected |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| OVF | SYNCRDY | CMP0 | |||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 |
Bit 7 – OVF Overflow Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Overflow Interrupt Enable bit and enable the Overflow interrupt.
| Value | Description |
|---|---|
| 0 | The Overflow interrupt is disabled |
| 1 | The Overflow interrupt is enabled |
Bit 6 – SYNCRDY Synchronization Ready Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Synchronization Ready Interrupt Enable bit and enable the Synchronization Ready interrupt.
| Value | Description |
|---|---|
| 0 | The Synchronization Ready interrupt is disabled |
| 1 | The Synchronization Ready interrupt is enabled |
Bit 0 – CMP0 Compare 0 Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Compare 0 Interrupt Enable bit and enable the Compare 0 interrupt.
| Value | Description |
|---|---|
| 0 | The Compare 0 interrupt is disabled |
| 1 | The Compare 0 interrupt is enabled |