16.7.3 Event Control - MODE0

Table 16-4. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
R Readable bit HC Cleared by Hardware(Grey cell)Unimplemented
W Writable bit HS Set by Hardware X Bit is unknown at Reset
K Write to clear S Software settable bit
Name: EVCTRL
Offset: 0x04
Reset: 0x0000
Property: Enable-Protected, Write-Protected

Bit 15141312111098 
 OVFEO      CMPEO0 
Access R/WR/W 
Reset 00 
Bit 76543210 
 PEREOx PEREOx PEREOx PEREOx PEREOx PEREOx PEREOx PEREOx  
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bit 15 – OVFEO Overflow Event Output Enable

ValueDescription
0Overflow event is disabled and will not be generated
1Overflow event is enabled and will be generated for every overflow

Bit 8 – CMPEO0 Compare 0 Event Output Enable

ValueDescription
0Compare 0 event is disabled and will not be generated
1Compare 0 event is enabled and will be generated for every compare match

Bits 7,6,5,4,3,2,1,0 – PEREOx  Periodic Interval x Event Output Enable [x=7:0]

ValueDescription
0Periodic Interval x event is disabled and will not be generated
1Periodic Interval x event is enabled and will be generated