17.7.5 Event Control
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | EVCTRL |
| Offset: | 0x04 |
| Reset: | 0x00000000 |
| Property: | Write-Protected |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| EXTINTEO15 | EXTINTEO14 | EXTINTEO13 | EXTINTEO12 | EXTINTEO11 | EXTINTEO10 | EXTINTEO9 | EXTINTEO8 | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| EXTINTEO7 | EXTINTEO6 | EXTINTEO5 | EXTINTEO4 | EXTINTEO3 | EXTINTEO2 | EXTINTEO1 | EXTINTEO0 | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 – EXTINTEO External Interrupt x Event Output Enable [x=15..0]
These bits indicate whether the event associated with the EXTINTx pin is enabled or not to generated for every detection.
| Value | Description |
|---|---|
| 0 | Event from pin EXTINTx is disabled. |
| 1 | Event from pin EXTINTx is enabled. |