12.10.13 PIR4

Peripheral Interrupt Request Register 4

Note:

RC1IF is read-only. User software must read RC1REG to clear RC1IF.
TX1IF is read-only. User software must load TX1REG to clear TX1IF. TX1IF does not indicate a completed transmission (use TMRT for this purpose instead).
Interrupt flag bits are set when an Interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable (GIE) bit. User software may ensure the appropriate interrupt flag bits are cleared before enabling an interrupt.

Name:	PIR4
Offset:	0x0090


Bit	7	6	5	4	3	2	1	0
	RC1IF	TX1IF	CLC4IF	CLC3IF	CLC2IF	CLC1IF	CWG1IF	NCO1IF
Access	R	R	R/W/HS	R/W/HS	R/W/HS	R/W/HS	R/W/HS	R/W/HS
Reset	0	0	0	0	0	0	0	0

Bit 7 – RC1IF EUSART1 Receive Interrupt Flag⁽¹⁾

Value	Description
1	The EUSART1 receive buffer (RC1REG) is not empty (contains at least one byte)
0	The EUSART1 receive buffer is empty

Bit 6 – TX1IF EUSART1 Transmit Interrupt Flag⁽²⁾

Value	Description
1	The EUSART1 transmit buffer (TX1REG) is empty
0	The EUSART1 transmit buffer is not empty

Bit 5 – CLC4IF CLC4 Interrupt Flag

Value	Description
1	CLC4 interrupt has occurred (must be cleared in software)
0	CLC4 interrupt event has not occurred

Bit 4 – CLC3IF CLC3 Interrupt Flag

Value	Description
1	CLC3 interrupt has occurred (must be cleared in software)
0	CLC3 interrupt event has not occurred

Bit 3 – CLC2IF CLC2 Interrupt Flag

Value	Description
1	CLC2 interrupt has occurred (must be cleared in software)
0	CLC2 interrupt event has not occurred

Bit 2 – CLC1IF CLC1 Interrupt Flag

Value	Description
1	CLC1 interrupt has occurred (must be cleared in software)
0	CLC1 interrupt event has not occurred

Bit 1 – CWG1IF CWG1 Interrupt Flag

Value	Description
1	CWG1 interrupt has occurred (must be cleared in software)
0	CWG1 interrupt event has not occurred

Bit 0 – NCO1IF NCO1 Interrupt Flag

Value	Description
1	NCO1 interrupt has occurred (must be cleared in software)
0	NCO1 interrupt event has not occurred

RC1IF is read-only. User software must read RC1REG to clear RC1IF. TX1IF is read-only. User software must load TX1REG to clear TX1IF. TX1IF does not indicate a completed transmission (use TMRT for this purpose instead). Interrupt flag bits are set when an Interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable (GIE) bit. User software may ensure the appropriate interrupt flag bits are cleared before enabling an interrupt.