12.10.7 PIE5
Note: Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt controlled by registers PIE1 through
PIE6.
| Name: | PIE5 |
| Offset: | 0x009B |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CM2IE | CM1IE | BCL2IE | SSP2IE | BCL1IE | SSP1IE | RC2IE | TX2IE | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 7 – CM2IE Comparator 2 Interrupt Enable
| Value | Description |
|---|---|
| 1 | Comparator 2 interrupts are enabled |
| 0 | Comparator 2 interrupts are disabled |
Bit 6 – CM1IE Comparator 1 Interrupt Enable
| Value | Description |
|---|---|
| 1 | Comparator 1 interrupts are enabled |
| 0 | Comparator 1 interrupts are disabled |
Bit 5 – BCL2IE MSSP2 Bus Collision Interrupt Enable
| Value | Description |
|---|---|
| 1 | MSSP2 Bus Collision interrupts are enabled |
| 0 | MSSP2 Bus Collision interrupts are disabled |
Bit 4 – SSP2IE MSSP2 Interrupt Enable
| Value | Description |
|---|---|
| 1 | MSSP2 interrupts are enabled |
| 0 | MSSP2 interrupts are disabled |
Bit 3 – BCL1IE MSSP1 Bus Collision Interrupt Enable
| Value | Description |
|---|---|
| 1 | MSSP1 Bus Collision interrupts are enabled |
| 0 | MSSP1 Bus Collision interrupts are disabled |
Bit 2 – SSP1IE MSSP1 Interrupt Enable
| Value | Description |
|---|---|
| 1 | MSSP1 interrupts are enabled |
| 0 | MSSP1 interrupts are disabled |
Bit 1 – RC2IE EUSART2 Receive Interrupt Enable
| Value | Description |
|---|---|
| 1 | EUSART2 receive interrupts are enabled |
| 0 | EUSART2 receive interrupts are disabled |
Bit 0 – TX2IE EUSART2 Transmit Interrupt Enable
| Value | Description |
|---|---|
| 1 | EUSART2 transmit interrupts are enabled |
| 0 | EUSART2 transmit interrupts are disabled |