2.7.2 Acknowledge

The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter, whereas the host generates an extra acknowledge related clock pulse. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge-related clock pulse; setup and hold times must be taken into account.

A target receiver which is addressed must generate an acknowledge after the reception of each byte.

Also, a host receiver must generate an acknowledge after the reception of each byte that has been clocked out of the target transmitter, except on the last received byte. A host receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the target transmitter. In this event, the transmitter must leave the data line HIGH to enable the host to generate a STOP condition.