9.6.2 Edge_Anchors for Memory Placement
(Ask a Question)The PolarFire silicon architecture requires that the Memory interface be
placed in specific and pre-defined locations of the chip to achieve optimal QOR and timing
performance. These specific location are called Edge_Anchors and are used to identify the
specific location in the PolarFire chip for optimal Memory Interface I/O placement. See the
PolarFire Family Memory Controller User Guide
for a mapping of DDR memory interface types to Edge_Anchor locations. The
Edge_Anchors are as follows:
- NORTH_NE
- NORTH_NW
- SOUTH_SE
- SOUTH_SW
- WEST_NW
- WEST_SW
The ports for each Edge_Anchor is represented by a different color for easy identification. The list of possible Edge_Anchors is context-sensitive to the Memory Interface type and represents the legal and optimal locations for the specific Memory interface type. The list of Edge_Anchors for DDR4, for example, is different from the list for DD2/DDR3. DDR4 has fewer locations (Edge_Anchors) for I/O placement than DDR2/DD3.