20.1.2.2 Interrupts

The MSS simulation model acknowledges assertion of the F2H interrupts. There are 64 F2H interrupt ports. When the MSS receives a valid active-high interrupt, it acknowledges them by printing a message as shown in the following code block.

# INFO : F2H_INTERRUPT[0] is asserted
# INFO : F2H_INTERRUPT[1] is asserted
# INFO : F2H_INTERRUPT[2] is asserted
# INFO : F2H_INTERRUPT[3] is asserted
# INFO : F2H_INTERRUPT[4] is asserted
# INFO : F2H_INTERRUPT[5] is asserted
# INFO : F2H_INTERRUPT[6] is asserted
# INFO : F2H_INTERRUPT[7] is asserted
# INFO : F2H_INTERRUPT[8] is asserted
# INFO : F2H_INTERRUPT[9] is asserted
# INFO : F2H_INTERRUPT[10] is asserted

# ERROR : F2H_INTERRUPT[0] must stay high for at least one MSS clock cycle
# ERROR : F2H_INTERRUPT[1] must stay high for at least one MSS clock cycle
# ERROR : F2H_INTERRUPT[2] must stay high for at least one MSS clock cycle
# ERROR : F2H_INTERRUPT[3] must stay high for at least one MSS clock cycle
# ERROR : F2H_INTERRUPT[4] must stay high for at least one MSS clock cycle
# ERROR : F2H_INTERRUPT[5] must stay high for at least one MSS clock cycle
# ERROR : F2H_INTERRUPT[6] must stay high for at least one MSS clock cycle
# ERROR : F2H_INTERRUPT[7] must stay high for at least one MSS clock cycle
# ERROR : F2H_INTERRUPT[8] must stay high for at least one MSS clock cycle
# ERROR : F2H_INTERRUPT[9] must stay high for at least one MSS clock cycle

vsim -L polarfire -L presynth -t 1ps -g H2F_MEMFILE=(path)/*.txt presynth.tb

vsim -L polarfire -L presynth -t 1ps -g H2F_MEMFILE=E:/mss_sim/h2f_sim.txt presynth.tb

Wait Time        (Time to wait in number MSS PLL clock cycles, Hex)
Interrupt Value  (16-bit value, Hex)
Wait time        (Time to wait in number MSS PLL clock cycles, Hex)
Interrupt Value  (16-bit value, Hex)
...

Example:

100          (Wait for 100 (256 in DEC) MSS PLL clock cycles)
FFFF         (Set all 16 interrupts)
1000         (Wait for 1000 (4096 in DEC) MSS clock cycles)
0000         (Clear all 16 interrupts)
...

The H2F interrupts can be cleared by clearing an interrupt register bit in the corresponding peripheral. These AXI transactions can be generated by an Initiator in FPGA fabric.