20.1.2.1 FIC Interface

The PolarFire SoC FPGA provides multiple FICs to enable connectivity between user logic in the FPGA fabric and the MSS. FIC is part of the MSS and acts as a bridge between the MSS and the FPGA fabric. The initiator FIC interface provides access to the address range listed in the following table.

Table 20-1. FIC Interface Address Ranges
FIC InterfaceNumber of RegionsStart AddressEnd AddressSize

FIC0

2

0x6000_0000

0x7FFF_FFFF

512 MB

0x20_0000_0000

0x2F_FFFF_FFFF

64 GB

FIC1

2

0xE000_0000

0xFFFF_FFFF

512 MB

0x30_0000_0000

0x3F_FFFF_FFFF

64 GB

FIC3

1

0x4000_0000

0x5FFF_FFFF

512 MB

Note: 64-bit BFM instructions shall not be used in FIC-3 (PFSOC_MSS_FIC3).

The initiator FIC allows and initiates the AXI transaction only when addresses entered in the BFM file are within the dedicated address range. Otherwise, it shows a DRC in the simulation log.

The target FIC responds to AXI initiator in fabric in the following way:

  • Uses AXI transaction details to clear interrupts and provides a valid AXI response.
  • Provides a transparent connection between the AXI switch and FIC interface to access the DDR controller and DDR memory.
  • Prints a message in the simulation log in case of incorrect addressing for other addresses.
Note: The DLL in the MSS FIC interface is always bypassed in simulation. MSS_FIC_x_DLL_LOCK_M2F output is not driven (always Tri-State) in the simulation model.

20.1.2.1.1 BFM Commands

Libero generates BFM files for FIC interfaces as shown in the following table.

Table 20-2. FIC Interface BFM Files
ModuleBFM File Name
FIC0PFSOC_MSS_FIC0
FIC1PFSOC_MSS_FIC1
FIC3PFSOC_MSS_FIC3
FIC4

PFSOC_MSS_FIC4

Note: PFSOC_MSS_FIC4 BFM is created for only S devices.

The following figure shows the BFM files that can be accessed from within the simulation folder in the Libero tool.

Figure 20-3. BFM Files in the Simulation Folder

All BFM commands specified in Microchip DirectCore AMBA BFM User's Guide and SmartFusion 2, IGLOO 2, RTG4, PolarFire, and PolarFire SoC FPGA High Speed Serial Interface Simulation User Guide can be used to simulate the MSS.

The following code block shows a typical BFM instructions.

#=========================================================== 
# Enter your BFM commands in this file. 
# 
# Syntax: 
# ------- 
# 
# memmap resource_name base_address; 
# 
# write width resource_name byte_offset data; 
# read width resource_name byte_offset; 
# readcheck width resource_name byte_offset data; 
# 
#=========================================================== 
procedure main;
 
#FIC0 38bit Initiator Address declaration commands with memmap below 
memmap FPR_BASE_ADDR_38bit 0x2060000000; 
memmap FPR_BASE_ADDR_38bit_0 0x20600f0000; 
memmap FPR_BASE_ADDR_38bit_1 0x20fffffff8;
 
#FIC0 32bit Initiator Address declaration commands with memmap below 
memmap FPR_BASE_ADDR_int 0x60000000; 
memmap FPR_BASE_ADDR_int_0 0x60003000; 
memmap FPR_BASE_ADDR_int_1 0x60080000; 
memmap FPR_BASE_ADDR_int_2 0x68000000;
 
#Array creation command below 
int array[100];
 
#Creating table command below 
table LEGALISATION 0x0000 0x0000 0x0000 0x0000 \ 
0x0000 0x0000 0xffff 0xffff \ 
0xffff 0xfffd 0xfe01 0xfff2 \ 
0xffff 0xfffd 0xfe05 0xffff
 
#Signal declaration command below 
int u; 
int l;
 
#Writing data command below
write64     w FPR_BASE_ADDR_38bit_1 0x8 0x32323232 0xaaaaaaaa 
#Reading data command below
read64      w FPR_BASE_ADDR_38bit_1 0x8 
#Reading and checking data command below 
readcheck64 w FPR_BASE_ADDR_38bit_1 0x8 0x32323232 0xaaaaaaaa
 
#Writing data command below 
write64     w FPR_BASE_ADDR_38bit 0x0 0x10102020 0xaaaaaaaa
 
#Writing data command below 
write       w 0x70000000 0x0 0x10102020 
#Reading data command below 
read w 0x70000000 0x0 
#Reading and checking data command below 
readcheck w 0x70000000 0x0 0x10102020 
#Writing data command below 
write h 0x70000000 0x32 0xdddd 
#Reading data command below 
read h 0x70000000 0x32 
#Reading and checking data command below 
readcheck h 0x70000000 0x32 0xdddd 
#Writing data command below 
write b 0x70000000 0x64 0xee 
#Reading data command below 
read b 0x70000000 0x64 
#Reading and checking data command below 
readcheck b 0x70000000 0x64 0xee 

#Writing data command below 
write w FPR_BASE_ADDR_int 0x0 0x10102020 
#Reading data command below 
read w FPR_BASE_ADDR_int 0x0 
#Reading and checking data command below 
readcheck w FPR_BASE_ADDR_int 0x0 0x10102020 
#Reading data and store command below 
readstore x FPR_BASE_ADDR_int 0x0 u 
#Reading data and masking command below 
readmask x FPR_BASE_ADDR_int 0x0 0x10102020 0xFFFFFFFF 

#Writing burst data command below 
writemult w FPR_BASE_ADDR_int_0 0x0 0xFFFFFFFF 0xEEEEEEEE 0xAAAAAAAA 0xBBBBBBBB 0xCCCCCCCC 
#Reading burst data command below 
readmult w FPR_BASE_ADDR_int_0 0x0 5 
#Reading and checking burst data command below 
readmultchk w FPR_BASE_ADDR_int_0 0x0 0xFFFFFFFF 0xEEEEEEEE 0xAAAAAAAA 0xBBBBBBBB 0xCCCCCCCC
 
#masking of poll data command below 
pollmask w FPR_BASE_ADDR_int 0x0 0x10102020 0xFFFFFFFF 
#position of pollbit command below 
pollbit w FPR_BASE_ADDR_int 0x0 5 0x1 
#creating poll data command below 
poll w FPR_BASE_ADDR_int 0x0 0x10102020 
#filling data command below 
fill w FPR_BASE_ADDR_int 0x40 3 0x00000000 0x0 
#writing data to table command below 
writetable w FPR_BASE_ADDR_int 0x100 LEGALISATION 4 
#writing to array command below 
writearray w FPR_BASE_ADDR_int 0x120 array[0] 1 
#After filling check the data command below 
fillcheck w FPR_BASE_ADDR_int 0x40 3 0x00000000 0x0 
#reading table of data command below 
readtable w FPR_BASE_ADDR_int 0x100 LEGALISATION 4 
#reading array command below readarray w FPR_BASE_ADDR_int 0x120 array[0] 1 
#ahb cycle command below 
ahbcycle w FPR_BASE_ADDR_int_1 0x0 0xBBBBBBBB 0x0 
#memory testing command below 
memtest FPR_BASE_ADDR_int_2 0x0 0x4 0x0 0x0 0x2
 
#Writing data command below 
write64 w FPR_BASE_ADDR_38bit 0x0 0x10102020 0xaaaaaaaa 
#Reading data command below 
read64 w FPR_BASE_ADDR_38bit 0x0 
#Reading and checking data command below 
readcheck64 w FPR_BASE_ADDR_38bit 0x0 0x10102020 0xaaaaaaaa 
#Reading data and store command below
 
readstore64 x FPR_BASE_ADDR_38bit 0x0 u l 
#Display command below 
print "Lower 32bits = %h", l 
print "Upper 32bits = %h", u 
#Reading data and masking command below 
readmask64 x FPR_BASE_ADDR_38bit 0x0 0x10102020 0xaaaaaaaa 0xFFFFFFFF 0x0000FFFF
 
#Reading data and store command below 
readstore64 x FPR_BASE_ADDR_38bit 0x0 u l 
#Display command below 
print "Lower 32bits = %h", l 
print "Upper 32bits = %h", u
 
#Writing burst data command below 
writemult64 w FPR_BASE_ADDR_38bit_0 0x0 0xFFFFFFFF 0xEEEEEEEE 0xAAAAAAAA 0xBBBBBBBB 0xCCCCCCCC 0xDDDDDDDD 0x01010101 0x02020202 0x03030303 0xBADCAD00 
#Reading burst data command below 
readmult64 w FPR_BASE_ADDR_38bit_0 0x0 5 
#Reading and checking burst data command below 
readmultchk64 w FPR_BASE_ADDR_38bit_0 0x0 0xFFFFFFFF 0xEEEEEEEE 0xAAAAAAAA 0xBBBBBBBB 0xCCCCCCCC 0xDDDDDDDD 0x01010101 0x02020202 0x03030303 0xBADCAD00 

return

After adding a testbench to the design, you can use these BFM files to perform an MSS simulation by launching the Pre-Synth simulation.

The following is an example of a simulation log listing the BFM transactions.

#############################################################################
#  
# PFSOC_FIC_0_BFM:45:read64 w 00000021 00000000 at 105 ns
# PFSOC_FIC_0_BFM:47:readcheck64 w 00000021 00000000 32323232 at 2863311530 ns                 108
# PFSOC_FIC_0_BFM: Data Write 2100000000 32323232aaaaaaaa
# PFSOC_FIC_0_BFM:50:write64 w 00000020  60000000 10102020 aaaaaaaa at 248 ns
# PFSOC_FIC_0_BFM: Data Read 2100000000 32323232aaaaaaaa at 385.077000ns
# PFSOC_FIC_0_BFM:53:write w 00000000 70000000 10102020 at 388 ns
# PFSOC_FIC_0_BFM: Data Read 2100000000 32323232aaaaaaaa MASK:ffffffffffffffff at 525.105000ns
# PFSOC_FIC_0_BFM:55:read w 00000000 70000000 at 528 ns
# PFSOC_FIC_0_BFM: Data Write 2060000000 10102020aaaaaaaa
# PFSOC_FIC_0_BFM:57:readcheck w 00000000 70000000 10102020 at 668 ns
# PFSOC_FIC_0_BFM: Data Write 70000000 0000000010102020
# PFSOC_FIC_0_BFM:59:write h 00000000 70000032 0000dddd at 808 ns
# PFSOC_FIC_0_BFM: Data Read 70000000 1010202010102020 at 945.189000ns
# PFSOC_FIC_0_BFM:61:read h 00000000 70000032 at 949 ns
# PFSOC_FIC_0_BFM: Data Read 70000000 1010202010102020 MASK:00000000ffffffff at 1085.217000ns
# PFSOC_FIC_0_BFM:63:readcheck h 00000000 70000032 0000dddd at 1089 ns
# PFSOC_FIC_0_BFM: Data Write 70000032 00000000dddd0000
# PFSOC_FIC_0_BFM:65:write b 00000000 70000064 000000ee at 1229 ns
# PFSOC_FIC_0_BFM: Data Read 70000032 xxxxxxxxddddxxxx at 1365.273000ns
# PFSOC_FIC_0_BFM:67:read b 00000000 70000064 at 1369 ns
# PFSOC_FIC_0_BFM: Data Read 70000032 xxxxxxxxddddxxxx MASK:00000000ffff0000 at 1505.301000ns
# PFSOC_FIC_0_BFM:69:readcheck b 00000000 70000064 000000ee at 1509 ns
# PFSOC_FIC_0_BFM: Data Write 70000064 00000000000000ee
# PFSOC_FIC_0_BFM:72:write w 00000000 60000000 10102020 at 1649 ns
# PFSOC_FIC_0_BFM: Data Read 70000064 xxxxxxeexxxxxxxx at 1785.357000ns
# PFSOC_FIC_0_BFM:74:read w 00000000 60000000 at 1789 ns
# PFSOC_FIC_0_BFM: Data Read 70000064 xxxxxxeexxxxxxxx MASK:000000ff00000000 at 1925.385000ns
# PFSOC_FIC_0_BFM:76:readcheck w 00000000 60000000 10102020 at 1929 ns
# PFSOC_FIC_0_BFM: Data Write 60000000 0000000010102020
# PFSOC_FIC_0_BFM:79:readstore x 00000000 60000000 @101 at 2069 ns 
# PFSOC_FIC_0_BFM: Data Read 60000000 1010202010102020 at 2205.441000ns
# PFSOC_FIC_0_BFM: Data Read 60000000 1010202010102020 MASK:00000000ffffffff at 2345.469000ns
# PFSOC_FIC_0_BFM: Data Read 60000000 1010202010102020 at 2485.497000ns
# PFSOC_FIC_0_BFM:81:readmask x 00000000 60000000 10102020 ffffffff at 2492 ns
# PFSOC_FIC_0_BFM: (WARNING) writemult 32 bit command on 64 bit AXI bus is not allowed at 2495 ns
# PFSOC_FIC_0_BFM: (WARNING) readmult 32 bit command on 64 bit AXI bus is not allowed at 2499 ns
# PFSOC_FIC_0_BFM: (WARNING) readmultchk 32 bit command on 64 bit AXI bus is not allowed at 2502 ns
# PFSOC_FIC_0_BFM:92:pollmask w 00000000 60000000 10102020 ffffffff at 2506 ns
# PFSOC_FIC_0_BFM: Data Read 60000000 1010202010102020 MASK:00000000ffffffff at 2635.527000ns
# PFSOC_FIC_0_BFM: Data Read 60000000 1010202010102020 MASK:00000000ffffffff at 2785.557000ns
# PFSOC_FIC_0_BFM:94:pollbit w 00000000 60000000 5 1 at 2789 ns
# PFSOC_FIC_0_BFM: Data Read 60000000 1010202010102020 MASK:0000000000000020 at 2935.587000ns
# PFSOC_FIC_0_BFM:96:poll w 00000000 60000000 10102020 at 2939 ns
# PFSOC_FIC_0_BFM: Data Read 60000000 1010202010102020 MASK:00000000ffffffff at 3085.617000ns
# PFSOC_FIC_0_BFM:98:fill w 00000000 60000040 3 3 3 at 3089 ns
# PFSOC_FIC_0_BFM: Data Write 60000040 0000000000000000
# PFSOC_FIC_0_BFM:100:writetable w 00000000 60000100 7 4 at 3239 ns 
# PFSOC_FIC_0_BFM: Data Write 60000044 0000000000000000
# PFSOC_FIC_0_BFM: Data Write 60000048 0000000000000000
# PFSOC_FIC_0_BFM: Data Write 60000100 0000000000000000
# PFSOC_FIC_0_BFM: Data Write 60000104 0000000000000000
# PFSOC_FIC_0_BFM:102:writearray w 00000000 60000120 1 1 at 3799 ns 
# PFSOC_FIC_0_BFM: Data Write 60000108 0000000000000000
# PFSOC_FIC_0_BFM:104:fillcheck w 00000000 60000040 3 3 0 at 3939 ns
# PFSOC_FIC_0_BFM: Data Write 6000010c 0000000000000000
# PFSOC_FIC_0_BFM: Data Write 60000120 00000000xxxxxxxx
# PFSOC_FIC_0_BFM: Data Read 60000040 0000000000000000 MASK:00000000ffffffff at 4355.871000ns
# PFSOC_FIC_0_BFM:106:readtable w 00000000 60000100 7 4 at 4359 ns
# PFSOC_FIC_0_BFM: Data Read 60000044 0000000000000000 MASK:00000000ffffffff at 4495.899000ns
# PFSOC_FIC_0_BFM: Data Read 60000048 xxxxxxxx00000000 MASK:00000000ffffffff at 4635.927000ns
# PFSOC_FIC_0_BFM: Data Read 60000100 0000000000000000 MASK:00000000ffffffff at 4775.955000ns
# PFSOC_FIC_0_BFM: Data Read 60000104 0000000000000000 MASK:00000000ffffffff at 4915.983000ns
# PFSOC_FIC_0_BFM:108:readarray w 00000000 60000120 1 1 at 4919 ns
# PFSOC_FIC_0_BFM: Data Read 60000108 0000000000000000 MASK:00000000ffffffff at 5056.011000ns
# PFSOC_FIC_0_BFM:110:idle w 00000000 60080000 bbbbbbbb bbbbbbbb at 5059 ns
# PFSOC_FIC_0_BFM: Data Read 6000010c 0000000000000000 MASK:00000000ffffffff at 5196.039000ns
# PFSOC_FIC_0_BFM:112: memtest Started at 5199 ns
# PFSOC_FIC_0_BFM:  Address 00000000 68000000 Size 4 Cycles     0
# PFSOC_FIC_0_BFM: Data Read 60000120 xxxxxxxxxxxxxxxx at 5336.067000ns
# PFSOC_FIC_0_BFM: Data Write 60080000 00000000bbbbbbbb
# PFSOC_FIC_0_BFM: bfmtest complete  Writes 0  Reads 0  Nops 0
# PFSOC_FIC_0_BFM:115:write64 w 00000020  60000000 10102020 aaaaaaaa at 5349 ns
# PFSOC_FIC_0_BFM:117:read64 w 00000020 60000000 at 5353 ns
# PFSOC_FIC_0_BFM:119:readcheck64 w 00000020 60000000 10102020 at 2863311530 ns                5356
# PFSOC_FIC_0_BFM: Data Write 2060000000 10102020aaaaaaaa
# PFSOC_FIC_0_BFM:122:readstore64 x 00000020 60000000 @101 at 5499 ns 
# PFSOC_FIC_0_BFM: Data Read 2060000000 10102020aaaaaaaa at 5636.127000ns
# PFSOC_FIC_0_BFM: Data Read 2060000000 10102020aaaaaaaa MASK:ffffffffffffffff at 5776.155000ns
# PFSOC_FIC_0_BFM: Data Read 2060000000 10102020aaaaaaaa at 5916.183000ns
# PFSOC_FIC_0_BFM:Lower 32bits = aaaaaaaa
# PFSOC_FIC_0_BFM:Upper 32bits = 10102020
# PFSOC_FIC_0_BFM:128:readmask64 x 00000020 60000000 10102020 aaaaaaaa ffffffff 0000ffff at 5923 ns
# PFSOC_FIC_0_BFM:131:readstore64 x 00000020 60000000 @101 at 5926 ns 
# PFSOC_FIC_0_BFM: Data Read 2060000000 10102020aaaaaaaa MASK:ffffffff0000ffff at 6066.213000ns
# PFSOC_FIC_0_BFM: Data Read 2060000000 10102020aaaaaaaa at 6206.241000ns
# PFSOC_FIC_0_BFM:Lower 32bits = aaaaaaaa
# PFSOC_FIC_0_BFM:Upper 32bits = 10102020
# PFSOC_FIC_0_BFM:137:writemultiple64 x 00000020 600f0000 ffffffff ... at 6213 ns
# PFSOC_FIC_0_BFM: Data Write 20600f0000 ffffffffeeeeeeee
# PFSOC_FIC_0_BFM: Data Write 20600f0008 aaaaaaaabbbbbbbb
# PFSOC_FIC_0_BFM: Data Write 20600f0010 ccccccccdddddddd
# PFSOC_FIC_0_BFM:139:readmult64 x 00000020 600f0000 10 at 6230 ns
# PFSOC_FIC_0_BFM: Data Write 20600f0018 0101010102020202
# PFSOC_FIC_0_BFM: Data Write 20600f0020 03030303badcad00
# PFSOC_FIC_0_BFM: Data Read 20600f0000 ffffffffeeeeeeee at 6536.307000ns
# PFSOC_FIC_0_BFM: Data Read 20600f0008 aaaaaaaabbbbbbbb at 6546.309000ns
# PFSOC_FIC_0_BFM: Data Read 20600f0010 ccccccccdddddddd at 6556.311000ns
# PFSOC_FIC_0_BFM:141:readmultchk64 x 00000020  600f0000 ffffffff ... at 6560 ns
# PFSOC_FIC_0_BFM: Data Read 20600f0018 0101010102020202 at 6566.313000ns
# PFSOC_FIC_0_BFM: Data Read 20600f0020 03030303badcad00 at 6576.315000ns
# PFSOC_FIC_0_BFM: Data Read 20600f0000 ffffffffeeeeeeee MASK:ffffffffffffffff at 6716.343000ns
# PFSOC_FIC_0_BFM: Data Read 20600f0008 aaaaaaaabbbbbbbb MASK:ffffffffffffffff at 6726.345000ns
# PFSOC_FIC_0_BFM: Data Read 20600f0010 ccccccccdddddddd MASK:ffffffffffffffff at 6736.347000ns
# PFSOC_FIC_0_BFM:144:return
# PFSOC_FIC_0_BFM: Data Read 20600f0018 0101010102020202 MASK:ffffffffffffffff at 6746.349000ns
# PFSOC_FIC_0_BFM: Data Read 20600f0020 03030303badcad00 MASK:ffffffffffffffff at 6756.351000ns
#############################################################################
#  
# FIC_0 BFM Simulation Complete - 50 Instructions - NO ERRORS
#  
#############################################################################
The FIC BFM initiator can also be used to mimic the DMA type burst data transfer between MSS and fabric. With this, you may want to check the response of fabric RTL by transferring data to/from GEM (IP/Ethernet packet), USB, and so on.

When data transfer is from MSS to fabric, source address can be any initiator within the MSS and destination address must be within the corresponding FIC address range as per Table 2-1. FIC Interface Address Ranges. As FIC BFM represents all the initiators of MSS to communicate with the fabric, so the source data can be provided through the vec file. This vec file is read by BFM initiator and it transfers the data to the fabric through AXI write transactions. The BFM initiator considers the data from vec as AXI data and it is your responsibility to fill the vec file with proper packets like Ethernet, USB, and so on.

When data transfer is from fabric to MSS, source address should be within the corresponding FIC address range and the destination can be any address within MSS (Peripherals, memories, and so on). The FIC BFM transfers the data from fabric to MSS through the AXI read transactions and does not store this read data anywhere within the FIC/MSS.

The following table lists the BFM commands and sequence that to be used to perform DMA type transfer.
Table 20-3. BFM Commands And Sequence Used To Perform DMA Type Transfer
CommandFunction
setup 0x8 <source address> <destination address>To set source and destination address of DMA transfer
setup 0xA <data>To set DMA data source, where,

<data> = 0, means data increment by 1 starting from 0x1

<data> = 1, means random data

<data> = 2, means data from vec file

setup 0x9 <DMA_Length> <Control>To set DMA start and control, where,

set Control bit-0 to '1' to start DMA transfer

set Control bit-1 to '1' to transfer from MSS to Fabric (AXI write)

set Control bit-2 to '1' to transfer from Fabric to MSS (AXI read)

use Control = 0x3 to start DMA transfer from MSS to Fabric

use Control = 0x5 to start DMA transfer from Fabric to MSS

<DMA_Length> is hex value of number of bytes to transfer. Maximum allowed value is 4096 bytes.

The following code block shows a typical example to perform DMA type data transfer.
memmap GEM0  0x20110000;
memmap LSRAM 0x60000000;// Through FIC0

procedure main;

int dma_size;
set dma_size 0x100; //256 byte of dma size
print "*************************MSS DMA test*************************"
setup 0x8 GEM0 LSRAM // set source and destination address
setup 0xA 0x2 Din.vec // read data from vec file
setup 0x9 dma_size 0x3 //
wait 1us;
setup 0x9 dma_size 0x5
wait 1us;
return