9.8.2 DRC Rules
(Ask a Question)The I/O Editor enforces the following list of common Design Rules Check (DRC) rules:
- All I/Os of the same logical lane must be placed within the same physical lane.
- For any one physical lane, only one logical lane is allowed to be placed.
- Non-logical lane I/Os can be placed in any physical lane.
- For RGMII Interface, the *_RXC port must be placed on the CLKIN_S_* side of the physical lane.
- When the CDR is placed in a physical lane, the DQS_N slot is reserved and is not available for I/O placement.
For more information on DRC rules for the IOD I/O placement, see the PolarFire FPGA and PolarFire SoC FPGA User I/O User Guide.