20.2.2.3.10 Physical Memory Protection

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The Physical Memory Protection (PMP) prevents a process (running on a RISC-V Processor) or an initiator (FPGA Fabric) from accessing memory that has not been allocated to it. RISC-V system has PMP unit, which provides control registers for each processor to allow physical memory access privileges (read, write, execute) to be specified for each physical memory region.

For more information on how PMP works on RISC-V® processors, refer the RISC-V PMP - With PFSoC Examples page.

Similarly, the AXI Switch has Memory Protection Unit (MPU) block which provides register control to setup memory access regions for FPGA initiators.

Application Processor Initialization

The following figure shows the Application Processor Initialization tab.

Processor Initiators

Four CPU initiators can be enabled in one of the two Asymmetric Multi Processing (AMP) contexts. CPU initiators can access both CPU and Peripherals. However, they cannot be enabled in both Context A & Context B.

Processor Initiators in Context A and Context B can access the following selected Peripherals

The AMP Context A is assigned to AHB0 bus interface and AMP Context B is assigned to AHB1 bus interface. Peripherals can be enabled in either Context A or in Context B. The range and base address for the peripherals are populated in Graphical User Interface and are not editable. The base address will be different for peripherals that are on dual AHB bus interfaces for Context A and Context B.

Figure 20-48. Processor Initiators in Context A and Context B Accessing the Peripherals

Processor Initiators can access memory regions created as follows (DDR/FPGA Fabric memory through FICs)

DDR memory appears at several address ranges depending on whether it is cached, non-cached, or access through a Write Combine Buffer (WCB). WCB improves performance (by combining multiple writes to the same address into a single write) for sequential accesses. Each AMP context needs to specify how much DDR memory of each type it needs. Some DDR memories may be shared between AMP Context to pass data. User can create protection for memory region accessed by processors by clicking on the Add Memory Region... button. User can delete any memory region by selecting the memory region and clicking Delete button. The following figure shows the memory regions available to Processor Initiators.

Figure 20-49. Memory Regions Available to Processor Initiators.

The following table lists different types of memory regions that user can create.

Table 20-23. Available Memory Region
Memory Type	Memory Size	Address Size	Address Range
DDR Cached	512 MB	32-bit	0x80000000 - 0xBFFFFFFF
DDR Cached	16 GB	64-bit	0x10_00000000 - 0x13_FFFFFFFF
DDR Non-Cached	256 MB	32-bit	0xC0000000 - 0xCFFFFFFF
DDR Non-Cached	16 GB	64-bit	0x14_00000000 - 0x17_FFFFFFFF
DDR Non-Cached with WCB enabled	256 MB	32-bit	0xC0000000 - 0xCFFFFFFF
DDR Non-Cached with WCB enabled	16 GB	64-bit	0x14_00000000 - 0x17_FFFFFFFF
FIC_0 Memory	512 MB	32-bit	0x60000000 - 0x7FFFFFFF
FIC_0 Memory	64 GB	64-bit	0x20_00000000 - 0x2F_FFFFFFFF
FIC_1 Memory	512 MB	32-bit	0xE0000000 - 0xFFFFFFFF
FIC_1 Memory	64 GB	64-bit	0x30_00000000 - 0x3F_FFFFFFFF
Loosely Integrated Memory	—	—	Start Address is 0x0800_0000
Scratch	—	—	Start Address is 0x0A00_0000

When the values are modified for Peripherals and Memory Regions, the same gets updated dynamically in the PMPxCFG and CSRPMP_ADDx pairs in both the Context A and Context B tables.

Monitor Processor Initialization

The Monitor Processor Initialization view has a Monitor Processor Initialization tab with a default region, E51_Memory_Region_0. It can only be modified in the Expert Mode.

The following figure shows the Monitor Processor Initialization tab.

Figure 20-50. Monitor Processor Initialization Tab

Direct Memory Access

Direct Memory Access (DMA) provides FPGA (Non-CPU) Initiators read/write/execute access to the Memory subsystem and Fabric Memory. Users can create protection for memory regions accessed by FPGA Initiators by clicking any one of the FPGA Initiators and clicking the Add Memory Region... button. User can delete any memory region by selecting the memory region and clicking Delete button.

The following table lists the different types of memory regions that user can create.


Memory Type	Memory Size	Address Size	Address Range
DDR Non-Cached	256 MB	32-bit	0xC0000000 - 0xCFFFFFFF
DDR Non-Cached	16 GB	64-bit	0x14_00000000 - 0x17_FFFFFFFF
FIC_0 Memory	512 MB	32-bit	0x60000000 - 0x7FFFFFFF
FIC_0 Memory	64 GB	64-bit	0x20_00000000 - 0x2F_FFFFFFFF
FIC_1 Memory	512 MB	32-bit	0xE0000000 - 0xFFFFFFFF
FIC_1 Memory	64 GB	64-bit	0x30_00000000 - 0x3F_FFFFFFFF
FIC_3 Memory	512 MB	32-bit	0x40000000 - 0x5FFFFFFF
User Crypto Memory	128 KB	32-bit	0x22000000 - 0x2201FFFF

Expert Mode

Expert Mode is a specialized feature in the configurator intended for advanced users who require direct control over PMP and MPU configurations. It allows manual modification of these settings, overriding the automatic updates and calculations normally performed by the application. However, the Peripherals and Memory Regions tables do not update dynamically in this mode, nor can they be edited.

Expert Mode is applicable for the Application Processor Initialization, Monitor Processor Initialization and DMA tabs.

The following figure shows the Expert Mode in use in the Application Processor Initialization tab.

When the Expert Mode is disabled, all changes made are discarded and the values from the latest entries in the Initiator tables are displayed.

Note: In the Normal mode, when the Expert Mode option is unchecked, the PMP and MPU configation tables are read only. Any changes made in the Peripherals and Memory Regions tables are automatically calculated and reflected in the PMP and MPU tables.