3.4 Row Program

This algorithm (Table 3-4) programs one or more Flash rows. The row data will be preloaded into the device’s RAM. While the NVM controller programs/transfers the data from RAM to Flash, an additional row of data can be moved into device RAM for a subsequent Row Programming operation. By overlapping the transfer of data from the programmer to the device RAM, and from device RAM to Flash via the NVM controller, this programming algorithm attains maximal programming throughput approaching the raw clocking rate of the PGECx/PGEDx pins and should always be used when the source data are suitably aligned and big enough to define at least one row.

The Flash memory on these devices has a built-in Error Correcting Code (ECC) mechanism. The ECC checksum is calculated during a write operation and stored with data in Flash. If the Flash memory is programmed more than one time, this ECC checksum becomes corrupted. Next time, when the location with a corrupted checksum will be accessed, a single-bit ECC error interrupt or double-bit ECC error trap may be generated. After the Flash is erased, the programmer must not write any Flash location (including OTP areas) more then one time.

The Row Programming is disabled for User Configuration Ax and B areas, and will not have affect on them.

Table 3-4. Row Programming Algorithm
ICSP™ Sequence	ICSP Command Code	Data/Opcode	Instruction Executed
Step 1: Initialize pointers. Move VISI address to W8 and NVMCON address to W9.
`CMDEXEC`	`00`	`0xA0001F03`	`MOV.SL #VISI, W8`
`CMDEXEC`	`00`	`0xA400C003`	`MOV.SL #NVMCON, W9`
Step 2: Set W1 to a starting address in RAM (0x4000), then duplicate this pointer in W0 for `CMDSEQWR` use. Initialize NVMCON with 0x4002 to set up for Row Programming.
`CMDEXEC`	`00`	`0x84010003`	`MOV.SL #0x4000, W1`
`CMDEXEC`	`00`	`0x00000301`	`MOV.L W1, W0`
`CMDEXEC`	`00`	`0x8A900421`	`MOVS.W #0x4002, [W9]`
Step 3: Load data into the RAM buffer.
`CMDSEQWR`	`10`	Data[31:0]	`MOV.L #PGEDx<31:0>, [W0++]`
Step 4: Repeat Step 3 until all row data are moved to the RAM buffer. 128 total `CMDSEQWR` commands must be issued, each generating 32 bits of data for ascending RAM locations.
Step 5: To prepare for WR bit polling, move NVMCON to VISI.
`CMDEXEC`	`00`	`0x83892400`	`MOV.L [W9], [W8]`
Step 6: Move NVMCON to VISI. Shift VISI on PGEDx.
`CMDEXEC`	`00`	`0x83892400`	`MOV.L [W9], [W8]`
`CMDRD`	`01`	VISI
Step 7: Repeat Step 6 to poll the WR bit (NVMCON[15]) until it is clear, indicating completion of the previous Row Programming operation.
Step 8: Write the target Flash row address to NVMADR, the RAM source address to NVMSRCADR; then set the WR bit (NVMCON[15]) to begin hardware Row Programming.
`CMDEXEC`	`00`	`0x94030195`	`MOV.L W1, NVMSRCADR`
`CMDEXEC`	`00`	`0x8000C013`	`MOV.SL #NVMADR, W0`
`CMDSEQWR`	`10`	Destination Address[31:0]	`MOV.L #PGEDx<31:0>, [W0++]`
`CMDEXEC`	`00`	`0x8E900421`	`MOVS.W #0xC002, [W9]`
Step 9: Change the RAM buffer address to continue data loading while the NVM controller programs the previous buffer. The address will be switched between 0x4000 and 0x4200. Load the new starting address of the RAM buffer to W0.
`CMDEXEC`	`00`	`0x03014491`	`BTG.L W1, #9`
`CMDEXEC`	`00`	`0x03014491`	`MOV.L W1, W0`
Step 10: Repeat Steps 3-9 for any additional rows of data available for programming.
Step 11: To prepare for WR bit polling for the last Row Programming, move NVMCON to VISI.
`CMDEXEC`	`00`	`0x83892400`	`MOV.L [W9], [W8]`
Step 12: Move NVMCON to VISI. Shift VISI on PGEDx.
`CMDEXEC`	`00`	`0x83892400`	`MOV.L [W9], [W8]`
`CMDRD`	`01`	VISI
Step 13: Repeat Step 12 to poll the WR bit (NVMCON[15]) until it is clear, indicating programming completion for the last row.