3.6 CRC Checksum Calculation

This algorithm (Table 3-6) calculates the 32-bit Cyclic Redundancy Check (CRC) checksum of the Flash memory region. This checksum can be used to verify the written data in the previous programming steps or verify if the existing Flash contents match a known pattern, but which cannot be directly read due to code-protect or security restrictions defined in UCA or UCB. For details about the CRC calculation algorithm, refer to Flash Memory Controller.

The NVM controller CRC calculation can be disabled by Configuration Words in the User Configuration Ax and B areas.

Table 3-6. CRC Checksum Calculation Algorithm
ICSP™ Sequence	ICSP Command Code	Data/Opcode	Instruction Executed
Step 1: Move VISI address to W8 and NVMCRCCON address to W9. Set the CRCEN bit (NVMCRCCON[15]) to enable CRC hardware.
`CMDEXEC`	`00`	`0x9C00C163`	`MOV.SL #NVMCRCDATA, W7`
`CMDEXEC`	`00`	`0xA0001F03`	`MOV.SL #VISI, W8`
`CMDEXEC`	`00`	`0xA400C123`	`MOV.SL #NVMCRCCON, W9`
`CMDEXEC`	`00`	`0xC2F92008`	`BSET.L [W9], #15`
Step 2: Load the start address in the NVMCRCST register, the end address in the NVMCRCEND register and the initial value in the NVMCRCSEED register.
`CMDEXEC`	`00`	`0x8000C133`	`MOV.SL #NVMCRCST, W0`
`CMDSEQWR`	`10`	Start Address[31:0]	`MOV.L #PGEDx<31:0>, [W0++]`
`CMDSEQWR`	`10`	End Address[31:0]	`MOV.L #PGEDx<31:0>, [W0++]`
`CMDSEQWR`	`10`	Initial Value[31:0]	`MOV.L #PGEDx<31:0>, [W0++]`
Step 3: Set the START bit (NVMCRCCON[14]) to start the CRC calculation. Prepare for polling by moving NVMCRCCON to VISI.
`CMDEXEC`	`00`	`0xC2E92008`	`BSET.L [W9], #14`
`CMDEXEC`	`00`	`0x83892400`	`MOV.L [W9], [W8]`
Step 4: Move NVMCRCCON to VISI. Shift VISI on PGEDx.
`CMDEXEC`	`00`	`0x83892400`	`MOV.L [W9], [W8]`
`CMDRD`	`01`	VISI
Step 5: Repeat Step 4 to poll the START bit (NVMCRCCON[14]) until it is clear, indicating completion.
Step 6: Move NVMCRCOUT to VISI. Shift VISI on PGEDx.
`CMDEXEC`	`00`	`0x83872400`	`MOV.L [W7], [W8]`
`CMDEXEC`	`00`	`0x00000000`	`NOP`
`CMDRD`	`01`	VISI