3.3 Quadword Program

This algorithm (Table 3-3) programs one 16-byte aligned quadword. The Least Significant four bits of the destination address are “don't care” bits when written and will be forced to zeros for the programming operation. The Flash memory on these devices has a built-in Error Correcting Code (ECC) mechanism. The ECC checksum is calculated during write operations and stored and unmapped alongside each quadword. If the same Flash quadword is programmed more than one time without an intermediate erase cycle, this ECC checksum becomes corrupted. Subsequently, when the location with a corrupted checksum is read, an ECC error interrupt or trap will be generated. After the Flash is erased, the programmer must not write any Flash quadword location (including OTP areas) more then one time.

Table 3-3. Quadword Programming Algorithm
ICSP™ Sequence	ICSP Command Code	Data/Opcode	Instruction Executed
Step 1: Move VISI address to W8 and NVMCON address to W9.
`CMDEXEC`	`00`	`0xA0001F03`	`MOV.SL #VISI, W8`
`CMDEXEC`	`00`	`0xA400C003`	`MOV.SL #NVMCON, W9`
Step 2: Initialize W0 with the NVMCON address for sequential loading. Load the NVMCON value with the WR bit set in W10. Write 0x4001 in NVMCON to set up for Quadword Programming.
`CMDEXEC`	`00`	`0x00000309`	`MOV.L W9, W0`
`CMDEXEC`	`00`	`0xA8030007`	`MOV.SL #0xC001, W10`
`CMDSEQWR`	`10`	`0x00004001`	`MOV.L #PGEDx<31:0>, [W0++]`
Step 3: Load the destination address in NVMADR.
`CMDSEQWR`	`10`	Destination Address[31:0]	`MOV.L #PGEDx<31:0>, [W0++]`
Step 4: Load data in the NVM Controller Data registers (NVMDATA0, NVMDATA1, NVMDATA2 and NVMDATA3).
`CMDSEQWR`	`10`	Data[31:0]	`MOV.L #PGEDx<31:0>, [W0++]`
`CMDSEQWR`	`10`	Data[63:32]	`MOV.L #PGEDx<31:0>, [W0++]`
`CMDSEQWR`	`10`	Data[95:64]	`MOV.L #PGEDx<31:0>, [W0++]`
`CMDSEQWR`	`10`	Data[127:96]	`MOV.L #PGEDx<31:0>, [W0++]`
Step 5: Restore W0 with NVMCON’s address. Set the WR bit (NVMCON[15]) to start the NVM operation. Move NVMCON to VISI.
`CMDEXEC`	`00`	`0x1F0A0309`	`MOV.L W9, W0`
`CMDEXEC`	`00`	`0x1F0A0309`	`MOV.L W10, [W0++]`
`CMDEXEC`	`00`	`0x83892400`	`MOV.L [W9], [W8]`
Step 6: Move NVMCON to VISI. Shift VISI on PGEDx.
`CMDEXEC`	`00`	`0x83892400`	`MOV.L [W9], [W8]`
`CMDRD`	`01`	VISI
Step 7: Repeat Step 6 to poll the WR bit (NVMCON[15]) until it is clear, indicating completion.
Step 8: Repeat Steps 3-7 until all sequential quadwords have been programmed.