1.1 Flash Memory Controller

This Flash (or Nonvolatile Memory (NVM)) controller module performs the erase or write operations of the device Flash memory. The programming configuration and status are provided in the NVMCON register. The NVMOP[3:0] bits in the NVMCON register select the operation type. The descriptions of the available operations are listed in Table 1-3.

Table 1-3. Programming Operations
Type of Operation	NVMOP Bits (NVMCON[3:0]) Value	Description
Bulk Erase	`1110`	Erases the entire code and Configuration bits’ memories. OTP area(s) are not erased.
Inactive Partition Erase	`0100`	Erases the Inactive Partition.
Page Erase	`0011`	Erases a page of code or configuration memory. The address of the Flash page must be specified in the NVMADR register. NVMADR[11:0] are ignored (treated as all ‘`0`’s) for this NVMOP, hardware enforcing 4096-byte page alignment.
Row Write	`0010`	Writes a row of code or configuration memory. The address of the Flash row must be specified in the NVMADR register. The row data must be stored (prepared) in RAM. The address of the Flash data RAM buffer must be specified in the NVMSRCADR register. The Flash memory must be erased before the write operation. NVMADR[8:0] are hardware ignored, enforcing 512-byte destination row alignment. NVMSRCADR[1:0] are unimplemented, so source data in RAM must start on a 32-bit long word-aligned boundary.
Quadword Write	`0001`	Writes four 32-bit long words of code, OTP or configuration memory. The address of the Flash location to be written must be specified in the NVMADR register. The data must be stored (prepared) in the NVMDATA0, NVMDATA1, NVMDATA2 and NVMDATA3 registers. The Flash memory must be erased before the write operation. NVMADR[3:0] are unimplemented, enforcing 16-byte quadword address alignment.

The following steps should be done to erase or write the Flash memory:

Set the destination address to be erased or written in the NVMADR register.
Load data for the write operation in the NVMDATA0-NVMDATA3 registers or in a RAM buffer located by the address in the NVMSRCADR register.
Select the programming operation with the NVMOPx bits (NVMCON[3:0]).
Enable the NVM module operation by setting the WREN bit (NVMCON[14]).
Initiate the operation selected by setting the WR bit (NVMCON[15]).
Read/poll the WR bit (NVMCON[15]). The WR bit remains set while the erase or write operation is still in progress. Hardware clears this bit when the operation has completed. When the WR bit is cleared, the NVM interrupt flag (NVMCRCIF) is set.

The full description of the NVM controller and the programming details can be found in the device data sheet.

Also, the NVM controller can calculate a 32-bit Cyclic Redundancy Check (CRC) checksum. This checksum can be used to verify the result of Flash erase or programming. The start and end addresses of the Flash region are 4-Kbyte (page) aligned. The CRC can be calculated even while the Flash region is protected from data read-back.

The following steps should be done to get the CRC checksum:

Write the start address into the NVMCRCST register.
Write the end address into the NVMCRCEND register.
Enable the CRC by setting the CRCEN bit (NVMCRCCON[15]).
Start the calculation by setting the START bit (NVMCRCCON[14]).
Read/poll the START bit (NVMCRCCON[14]). This bit is cleared when the CRC checksum is ready. An interrupt flag, NVMCRCIF, is set when the CRC checksum is ready.
Read the CRC result from the NVMCRCDATA register.

Though the device hardware implements a parallel CRC-32 algorithm of the calculations, the same result can be achieved in the software by an algorithm using a 32-bit Shift register. The pseudocode in Shift Register CRC Calculation Algorithm explains the Shift register algorithm.

Shift Register CRC Calculation Algorithm

// Initialize shift register
SeedValue(31:0) = 0
ShiftRegister(31:0) = INVERT SeedValue(31:0)
REPEAT FOR ALL DATA WORDS
    REPEAT 32 TIMES
        // Exclusive OR of data bit 31 and shift register bit 0
        CRCNext = DataWord(31) EXOR ShiftRegister(0)
        // Shift the register right 
        ShiftRegister(30:0) = ShiftRegister(31:1)
        ShiftRegister(31) = 0
        // Shift data left to process the next bit of the word
        DataWord(31:1) = DataWord(30:0)
        IF CRCNext != 0 THEN
            // Exclusive OR with polynomial
            ShiftRegister(31:0) = ShiftRegister(31:0) EXOR 0xEDB88320
        ENDIF
    ENDREPEAT
ENDREPEAT
CRCResult = INVERT ShiftRegister(31:0)

Where:

SeedValue[31:0] – Initial CRC value with each bit value inverted, written to the NVMCRCSEED register. For a standard CRC-32 calculation, the NVMCRCIV register is configured to 0xFFFF_FFFF.
DataWord[31:0] – Current data word for the CRC calculation
CRCResult[31:0] – CRC checksum result in the NVMCRCDATA register