2.4.6 ADC Performance Degrades with CLKADC Above 1.5 MHz and VDD < 2.7V
The ADC INL performance degrades if CLKADC > 1.5 MHz and ADCn.CALIB.DUTYCYC is set to ‘0’ for VDD < 2.7V.
Work Around
None.
Affected Silicon Revisions
| Rev. A | Rev. B | Rev. C |
| X | X | X |
The ADC INL performance degrades if CLKADC > 1.5 MHz and ADCn.CALIB.DUTYCYC is set to ‘0’ for VDD < 2.7V.
None.
| Rev. A | Rev. B | Rev. C |
| X | X | X |