| Device | The Temperature Sensor is Not Calibrated on
Parts with Date Code 727, 728 and 1728 (Year 2017, Week 27/28) | - | X | - |
| Writing the OSCLOCK Fuse in FUSE.OSCCFG to
‘1’ Prevents Automatic Loading of Calibration Values | X | X | X |
| Write Operation Lost if Consecutive Writes
to Specific Address Spaces | X | X | X |
| AC | AC Interrupt Flag Not Set Unless Interrupt is
Enabled | X | - | - |
| False Triggers May Occur Under Certain
Conditions | X | - | - |
| ADC | One Extra Measurement Performed After
Disabling ADC Free-Running Mode | X | X | X |
| Changing ADC Control Bits During Free-Running
Mode not Working | X | - | - |
| ADC Wake-Up with WCMP | X | - | - |
| SAMPDLY and ASDV Does Not Work Together With
SAMPLEN | X | - | - |
| ADC Functionality Cannot be Ensured with
CLKADC Above 1.5 MHz and a Setting of 25% Duty Cycle | X | X | X |
| ADC Performance Degrades with
CLKADC Above 1.5 MHz and VDD < 2.7V | X | X | X |
| ADC Interrupt Flags Cleared When Reading
RESH | X | - | - |
| Pending Event Stuck When Disabling the
ADC | X | X | X |
| CCL | Connecting LUTs in Linked Mode Requires OUTEN
Set to ‘1’ | X | X | X |
| D-latch is Not Functional | X | X | X |
| The CCL Must be Disabled to Change the Configuration of a Single LUT | X | X | X |
| NVMCTRL | Wrong Reset Value of NVMCTRL.CTRLA
Register | X | X | X |
| PORTMUX | Selecting Alternative Output Pin for TCA0
Waveform Output 0-2 also Changes Waveform Output 3-5 | X | X | X |
| RTC | Any Write to the RTC.CTRLA Register Resets the
RTC and PIT Prescaler Counter | X | X | X |
| Disabling the RTC Stops the PIT | X | X | X |
| TCA | Restart Will Reset Counter Direction in
NORMAL and FRQ Mode | X | X | X |
| TCB | Minimum Event Duration Must Exceed the
Selected Clock Period | X | X | X |
| The TCB Interrupt Flag is Cleared When Reading
CCMPH | X | - | - |
| TCB Input Capture Frequency and Pulse-Width
Measurement Mode Not Working with Prescaled Clock | X | - | - |
| The TCA Restart Command Does Not Force a
Restart of TCB | X | X | X |
| CCMP and CNT Registers Act as 16-Bit
Registers in 8-Bit PWM Mode | X | X | X |
| TCD | Asynchronous Input Events Not Working When TCD Counter Prescaler is Used | X | X | X |
Halting TCD and Waiting for SW Restart Does
Not Work if Compare Value A is ‘0’ or Dual Slope Mode is Used | X | X | X |
| TWI | TIMEOUT Bit Field in the TWIn.MCTRLA Register
is Corrupted | X | - | - |
| TWI Smart Mode Gives Extra Clock Pulse | X | - | - |
| TWI Host Mode Wrongly Detects the Start Bit as
a Stop Bit | X | - | - |
| The TWI Host Enable Quick Command is Not
Accessible | X | - | - |
| USART | TXD Pin Override Not Released When Disabling
the Transmitter | X | X | X |
| Frame Error on a Previous Message May Cause
False Start Bit Detection | X | X | X |
| Full Range Duty Cycle Not Supported When
Validating LIN Sync Field | X | X | X |
| Open-Drain Mode Does Not Work When TXD is
Configured as Output | X | X | X |
