4.2 Synthesis/Simulation

The following table lists known issues and limitations associated with Synthesis/Simulation in the Libero SoC v2021.3.

Table 4-2. Known Issues and Limitations Associated with Synthesis/Simulation.
Family Description
AllWith the SynplifyPro R2021.03M release, when Synplfiy Pro is invoked on the Ubuntu platform, it lists packages/libraries on the terminal. This message can be safely ignored. Similarly, choosing Libero -> Edit Profile -> Synthesis lists packages/libraries on the Ubuntu platform. Click OK to proceed.
PolarFireLow data rate of 500Mbps/250Mhz fails in QDR II + Xtreme Device in simulation, but passes on the board.
AllIf multiple implementations are created in Libero/Synplify flow, each time the active implementation is switched, rerun synthesis for Libero to fetch the intended .vm netlist for active implementation.
PolarFire

When automatic compile point is enabled, synthesis passes successfully, but Place and Route errors-our and points to the derived constraint file: 

Error: SDC0025: C:\validate\PF_Mi_V_Tut\constraint\PROC_SUBSYSTEM_derived_constraints.sdc:17: Invalid false path constraint: the -through value [get_nets {AXI4_Interconnect_0/ARESETN* }] is incorrect.

Workaround: Turn the Automatic Compile Point OFF (unchecked) while running synthesis through the Libero -> Synthesis -> Configure Options dialog box. Keep the remaining options and all constraints as they are.

OR

Keep everything else the same, but update the *derived_constraints.sdc file to add the following line to use get_pins instead of get_nets:

set_false_path -through [ get_pins { AXI4_Interconnect_0/ARESETN* } ]