4.4 SmartDebug

The following table lists known issues and limitations associated with SmartDebug.

Table 4-4. Known Issues and Limitations Associated with SmartDebug
Family Description
PolarFire and PolarFire SoC

When Dual mode PCIe design is considered in SmartDebug, the following issues are observed in the PCIe debug feature:

  • Data Rate, Link Width, and other parameters are shown only for PCIe1, but not for the PCIe0.
PolarFire

Designs using DDR controller with FHB enabled may crash during the compiling stage with the following error message:

Internal Error:
Assertion Failed in:
“F:/release/sn/capture_sjsrvts05_mica_jen_sn/nsrc/hld/lib/gdevbase/src/gdev/gdevchip.cxx”, line 1598.
Please call technical support for assistance, providing the above diagnostic information