4.1 Libero

Table 4-1. Known Issues and Limitations Associated with Libero SoC v2021.3
Family	Description
PolarFire and PolarFire SoC	Non-recoverable zeroization mode is not programmed with Libero design, which does not have any POR digest configured and no custom security.
All	The `vdir` command used with ModelSim ME Pro 2021.3 for pre-compiled libraries on v2021.3 delivers the incorrect result of unknown version.
PolarFire	Simulations fail for system services when they look for `SNVM.mem` in Linux. Workaround: Rename `snvm.mem` to `SNVM.mem` to complete the simulation.
N/A	Identify debugger 2021-03M with Libero 2021.2 crashes on 11th generation Windows 10 machines.
SmartFusion2	Synthesis error occurs when trying to open encrypted HDL files on 11th generation Windows 10 machines.
IGLOO2, SmartFusion2 and RTG4	When the FDDR/MDDR is configured to support 4GB, it cannot access the entire 32-bit AXI address range. Designs that do not map the MSB of the 32-bit AXI address to the DDR memory address are not affected (that is, if the AXI address does not exceed a 2GB address space).
PolarFire	In the PolarFire DDR4 Configurator, users can enable both ECC and DM at the same time. These should be mutually exclusive selections.
PolarFire	Signal integrity settings from I/O editor have no effect on design implementation in Libero 2021.3.
IGLOO2	When all the keys (`UEK1`, `UEK2`, and `UEK3`) are disabled in keymode policy, ERASE and VERIFY actions fail with the following error message: The action 'ERASE' is not supported. You must select the programming action from this list: 'DEVICE_INFO, ENC_DATA_AUTHENTICATION, PROGRAM, READ_DEVICE_CERTIFICATE, READ_IDCODE'. The action 'VERIFY' is not supported. You must select the programming action from this list: 'DEVICE_INFO, ENC_DATA_AUTHENTICATION, PROGRAM, READ_DEVICE_CERTIFICATE, READ_IDCODE'. Workaround: Do not run ERASE and VERIFY actions when all the keys (`UEK1`, `UEK2`, and `UEK3`) are disabled in keymode policy.
PolarFire	Incorrect PUFT timing is reported when SPI Flash is using as an Initialization client.
All	If an Identify implementation was created through Libero project before another synthesis implementation (`synthesis_1`) is created through Libero -> Synthesis -> Configure Option, the next run `synthesis_1` command fails. Check the Active implementation dialog and confirm that there is no implementation in the pull-down menu. Trying to re-run it causes the Libero project to enter an unexpected stage. Workaround: Whenever Identify implementation is created through Libero -> Synthesis -> Configure Options, open SynplifyPro interactively, instrument the design, and run synthesis before running any synthesis or creating new implementation. Then return to Libero and create a new synthesis/identify implementation.
RTG4	When the Hold output in reset (output low) after power-up. Released and resynchronized with the PLL reference clock after the PLL locked option is set for the RTG4FCCCECALIB core, the clock appears at the output before the `LOCK` signal is asserted. Workaround: When synchronizer is used for the `LOCK` signal, do not use the `GLx` output clock. For example, you can use the free-running clock `CLK_50MHz` to clock the synchronizer circuit. Use the output of the three-stage synchronizer to drive both the `LOCK` signal and the `GLx_Yx_EN` signal.
All	In Libero flow, when multiple identify implementations are created and run initially, an error message appears only in the synthesis log, but does not propagate to the Libero error log. The following error message appears in the Libero window: No instrumentation file found for Identify implementation. Please open SynplifyPro interactively to launch Identify Instrumentor
PolarFire	The following enhancement to Synthesis Compiler in this SynplfiyPro 2020.09MSp1 release (Libero v2021.1 release) is related to the initial value support for memory initialization and is not technology specific. Test cases with the MiV core fails in synthesis with the following error message: :"./component/work/MIV_RV32IMA_L1_AXI_C0/MIV_RV32IMA_L1_AXI_C0_0/core/miv_rv32ima_l1_axi_data_arrays_0_ext.v":81:24:81:38\|Loop iteration limit 2000 exceeded - add '// synthesis loop_limit 4000' before the loop construct Workaround: In the Libero graphical user interface, select the Synthesis > Configure Option > Additional Parameters box and set_option -looplimit 4000 OR Add the following `SYNPLIFY_OPTIONS` options, and then set this option and run synthesis. configure_tool -name {SYNTHESIZE} -params {BLOCK_MODE:false} -params {BLOCK_PLACEMENT_CONFLICTS:ERROR} -params {BLOCK_ROUTING_CONFLICTS:LOCK} -params {CLOCK_ASYNC:800} -params {CLOCK_DATA:5000} -params {CLOCK_GLOBAL:2} -params {PA4_GB_COUNT:24} -params {PA4_GB_MAX_RCLKINT_INSERTION:16} -params {PA4_GB_MIN_GB_FANOUT_TO_USE_RCLKINT:1000} -params {RAM_OPTIMIZED_FOR_POWER:0} -params {RETIMING:false} -params {SEQSHIFT_TO_URAM:0} -params {SYNPLIFY_OPTIONS: set_option -looplimit 4000} -params {SYNPLIFY_TCL_FILE:}
ALL	If a module is present in an include file, the file appears as a linked file inside the project. If there is a broken Global Include Path for such projects, the include file is also shown with a broken link. If the project is closed and re-created, the correct Global Include Path appears properly. If the Global Include path under Project Settings is changed, two links are shown for include file inside the project: one with the new Global Include Path as shown inside the project, and another that is the broken link with the previous Global Include Path. There is no issue with functionality, but an extra broken link is shown in the project. Remove this link when the Global Include Path in Project Settings is changed.
RTG4 and PolarFire	I/O Editor shows resistor pull for P and N pins when LVDS failsafe (Dynamic ODT) is enabled. For RTG4 and PolarFire families, the resistor pull information for P and N pins are shown as pull up or both as pull down. They should be pull up for one pin and pull down for the other pin. This is a display issue only that existed in the I/O Editor and the pin report since 11.9 SP3. Due to a software infrastructure limitation, the P and N sides cannot have different values. Regardless of the display issue, both P and N sides program correctly: If the `RES_PULL` is up on both sides, it means the N side is programmed as Down. If the `RES_PULL` is down on both sides, it means the N side is programmed as Up.

PolarFire and PolarFire SoC

Non-recoverable zeroization mode is not programmed with Libero design, which does not have any POR digest configured and no custom security.

All

The vdir command used with ModelSim ME Pro 2021.3 for pre-compiled libraries on v2021.3 delivers the incorrect result of unknown version.

PolarFire

Simulations fail for system services when they look for SNVM.mem in Linux.

Workaround: Rename snvm.mem to SNVM.mem to complete the simulation.

N/A

Identify debugger 2021-03M with Libero 2021.2 crashes on 11th generation Windows 10 machines.

SmartFusion2

Synthesis error occurs when trying to open encrypted HDL files on 11th generation Windows 10 machines.

IGLOO2, SmartFusion2 and RTG4

When the FDDR/MDDR is configured to support 4GB, it cannot access the entire 32-bit AXI address range. Designs that do not map the MSB of the 32-bit AXI address to the DDR memory address are not affected (that is, if the AXI address does not exceed a 2GB address space).

PolarFire

In the PolarFire DDR4 Configurator, users can enable both ECC and DM at the same time. These should be mutually exclusive selections.

PolarFire

Signal integrity settings from I/O editor have no effect on design implementation in Libero 2021.3.

IGLOO2

When all the keys (UEK1, UEK2, and UEK3) are disabled in keymode policy, ERASE and VERIFY actions fail with the following error message:

The action 'ERASE' is not supported. You must select the programming action from this list: 'DEVICE_INFO, ENC_DATA_AUTHENTICATION, PROGRAM, READ_DEVICE_CERTIFICATE, READ_IDCODE'.

The action 'VERIFY' is not supported. You must select the programming action from this list: 'DEVICE_INFO, ENC_DATA_AUTHENTICATION, PROGRAM, READ_DEVICE_CERTIFICATE, READ_IDCODE'.

Workaround: Do not run ERASE and VERIFY actions when all the keys (UEK1, UEK2, and UEK3) are disabled in keymode policy.

PolarFire

Incorrect PUFT timing is reported when SPI Flash is using as an Initialization client.

All

If an Identify implementation was created through Libero project before another synthesis implementation (synthesis_1) is created through Libero -> Synthesis -> Configure Option, the next run synthesis_1 command fails. Check the Active implementation dialog and confirm that there is no implementation in the pull-down menu. Trying to re-run it causes the Libero project to enter an unexpected stage.

Workaround: Whenever Identify implementation is created through Libero -> Synthesis -> Configure Options, open SynplifyPro interactively, instrument the design, and run synthesis before running any synthesis or creating new implementation. Then return to Libero and create a new synthesis/identify implementation.

RTG4

When the Hold output in reset (output low) after power-up. Released and resynchronized with the PLL reference clock after the PLL locked option is set for the RTG4FCCCECALIB core, the clock appears at the output before the LOCK signal is asserted.

Workaround: When synchronizer is used for the LOCK signal, do not use the GLx output clock. For example, you can use the free-running clock CLK_50MHz to clock the synchronizer circuit. Use the output of the three-stage synchronizer to drive both the LOCK signal and the GLx_Yx_EN signal.

All

In Libero flow, when multiple identify implementations are created and run initially, an error message appears only in the synthesis log, but does not propagate to the Libero error log. The following error message appears in the Libero window:

No instrumentation file found for Identify implementation.
Please open SynplifyPro interactively to launch Identify Instrumentor

PolarFire

The following enhancement to Synthesis Compiler in this SynplfiyPro 2020.09MSp1 release (Libero v2021.1 release) is related to the initial value support for memory initialization and is not technology specific. Test cases with the MiV core fails in synthesis with the following error message:

:"./component/work/MIV_RV32IMA_L1_AXI_C0/MIV_RV32IMA_L1_AXI_C0_0/core/miv_rv32ima_l1_axi_data_arrays_0_ext.v":81:24:81:38|Loop iteration limit 2000 exceeded - add '// synthesis loop_limit 4000' before the loop construct

Workaround: In the Libero graphical user interface, select the Synthesis > Configure Option > Additional Parameters box and set_option -looplimit 4000

OR

Add the following SYNPLIFY_OPTIONS options, and then set this option and run synthesis.

configure_tool -name {SYNTHESIZE} -params {BLOCK_MODE:false} -params {BLOCK_PLACEMENT_CONFLICTS:ERROR} -params {BLOCK_ROUTING_CONFLICTS:LOCK} -params {CLOCK_ASYNC:800} -params {CLOCK_DATA:5000} -params {CLOCK_GLOBAL:2} -params {PA4_GB_COUNT:24} -params {PA4_GB_MAX_RCLKINT_INSERTION:16} -params {PA4_GB_MIN_GB_FANOUT_TO_USE_RCLKINT:1000} -params {RAM_OPTIMIZED_FOR_POWER:0} -params {RETIMING:false} -params {SEQSHIFT_TO_URAM:0} -params {SYNPLIFY_OPTIONS: set_option -looplimit 4000} -params {SYNPLIFY_TCL_FILE:}

ALL

If a module is present in an include file, the file appears as a linked file inside the project. If there is a broken Global Include Path for such projects, the include file is also shown with a broken link. If the project is closed and re-created, the correct Global Include Path appears properly. If the Global Include path under Project Settings is changed, two links are shown for include file inside the project: one with the new Global Include Path as shown inside the project, and another that is the broken link with the previous Global Include Path. There is no issue with functionality, but an extra broken link is shown in the project. Remove this link when the Global Include Path in Project Settings is changed.

RTG4 and PolarFire

I/O Editor shows resistor pull for P and N pins when LVDS failsafe (Dynamic ODT) is enabled. For RTG4 and PolarFire families, the resistor pull information for P and N pins are shown as pull up or both as pull down. They should be pull up for one pin and pull down for the other pin. This is a display issue only that existed in the I/O Editor and the pin report since 11.9 SP3. Due to a software infrastructure limitation, the P and N sides cannot have different values.

Regardless of the display issue, both P and N sides program correctly:

If the RES_PULL is up on both sides, it means the N side is programmed as Down.
If the RES_PULL is down on both sides, it means the N side is programmed as Up.

Libero® SoC v2021.3

4.1 Libero